src/mesa/drivers/dri/i965/gen7_misc_state.c

   1 /*
   2  * Copyright © 2011 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include "intel_batchbuffer.h"
  25 #include "intel_mipmap_tree.h"
  26 #include "intel_regions.h"
  27 #include "intel_fbo.h"
  28 #include "brw_context.h"
  29 #include "brw_state.h"
  30 #include "brw_defines.h"
  31
  32 static void emit_depthbuffer(struct brw_context *brw)
  33 {
  34    struct intel_context *intel = &brw->intel;
  35    struct gl_context *ctx = &intel->ctx;
  36    struct gl_framebuffer *fb = ctx->DrawBuffer;
  37
  38    /* _NEW_BUFFERS */
  39    struct intel_renderbuffer *drb = intel_get_renderbuffer(fb, BUFFER_DEPTH);
  40    struct intel_renderbuffer *srb = intel_get_renderbuffer(fb, BUFFER_STENCIL);
  41
  42    intel_emit_depth_stall_flushes(intel);
  43
  44    /* Gen7 doesn't support packed depth/stencil */
  45    assert(srb == NULL || srb != drb);
  46
  47    if (drb == NULL) {
  48       uint32_t dw1 = BRW_DEPTHFORMAT_D32_FLOAT << 18;
  49       uint32_t dw3 = 0;
  50
  51       if (srb == NULL) {
  52          dw1 |= (BRW_SURFACE_NULL << 29);
  53       } else {
  54          struct intel_region *region = srb->mt->region;
  55
  56          /* _NEW_STENCIL: enable stencil buffer writes */
  57          dw1 |= ((ctx->Stencil.WriteMask != 0) << 27);
  58
  59          /* 3DSTATE_STENCIL_BUFFER inherits surface type and dimensions. */
  60          dw1 |= (BRW_SURFACE_2D << 29);
  61          dw3 = ((region->width - 1) << 4) | ((2 * region->height - 1) << 18);
  62       }
  63
  64       BEGIN_BATCH(7);
  65       OUT_BATCH(GEN7_3DSTATE_DEPTH_BUFFER << 16 | (7 - 2));
  66       OUT_BATCH(dw1);
  67       OUT_BATCH(0);
  68       OUT_BATCH(dw3);
  69       OUT_BATCH(0);
  70       OUT_BATCH(0);
  71       OUT_BATCH(0);
  72       ADVANCE_BATCH();
  73    } else {
  74       struct intel_region *region = drb->mt->region;
  75       uint32_t tile_x, tile_y, offset;
  76
  77       offset = intel_renderbuffer_tile_offsets(drb, &tile_x, &tile_y);
  78
  79       assert(region->tiling == I915_TILING_Y);
  80
  81       /* _NEW_DEPTH, _NEW_STENCIL */
  82       BEGIN_BATCH(7);
  83       OUT_BATCH(GEN7_3DSTATE_DEPTH_BUFFER << 16 | (7 - 2));
  84       OUT_BATCH(((region->pitch * region->cpp) - 1) |
  85                 (brw_depthbuffer_format(brw) << 18) |
  86                 (0 << 22) /* no HiZ buffer */ |
  87                 ((srb != NULL && ctx->Stencil.WriteMask != 0) << 27) |
  88                 ((ctx->Depth.Mask != 0) << 28) |
  89                 (BRW_SURFACE_2D << 29));
  90       OUT_RELOC(region->bo,
  91                 I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
  92                 offset);
  93       OUT_BATCH(((region->width - 1) << 4) | ((region->height - 1) << 18));
  94       OUT_BATCH(0);
  95       OUT_BATCH(tile_x | (tile_y << 16));
  96       OUT_BATCH(0);
  97       ADVANCE_BATCH();
  98    }
  99
 100    BEGIN_BATCH(4);
 101    OUT_BATCH(GEN7_3DSTATE_HIER_DEPTH_BUFFER << 16 | (4 - 2));
 102    OUT_BATCH(0);
 103    OUT_BATCH(0);
 104    OUT_BATCH(0);
 105    ADVANCE_BATCH();
 106
 107    if (srb == NULL) {
 108       BEGIN_BATCH(3);
 109       OUT_BATCH(GEN7_3DSTATE_STENCIL_BUFFER << 16 | (3 - 2));
 110       OUT_BATCH(0);
 111       OUT_BATCH(0);
 112       ADVANCE_BATCH();
 113    } else {
 114       BEGIN_BATCH(3);
 115       OUT_BATCH(GEN7_3DSTATE_STENCIL_BUFFER << 16 | (3 - 2));
 116       OUT_BATCH(srb->mt->region->pitch * srb->mt->region->cpp - 1);
 117       OUT_RELOC(srb->mt->region->bo,
 118                 I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
 119                 0);
 120       ADVANCE_BATCH();
 121    }
 122
 123    BEGIN_BATCH(3);
 124    OUT_BATCH(GEN7_3DSTATE_CLEAR_PARAMS << 16 | (3 - 2));
 125    OUT_BATCH(0);
 126    OUT_BATCH(0);
 127    ADVANCE_BATCH();
 128 }
 129
 130 /**
 131  * \see brw_context.state.depth_region
 132  */
 133 const struct brw_tracked_state gen7_depthbuffer = {
 134    .dirty = {
 135       .mesa = (_NEW_BUFFERS | _NEW_DEPTH | _NEW_STENCIL),
 136       .brw = BRW_NEW_BATCH,
 137       .cache = 0,
 138    },
 139    .emit = emit_depthbuffer,
 140 };