2 * Copyright © 2011 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 #include "brw_context.h"
25 #include "brw_state.h"
26 #include "brw_defines.h"
28 #include "main/macros.h"
29 #include "intel_batchbuffer.h"
32 upload_sbe_state(struct brw_context
*brw
)
34 struct intel_context
*intel
= &brw
->intel
;
35 struct gl_context
*ctx
= &intel
->ctx
;
36 /* CACHE_NEW_VS_PROG */
37 uint32_t num_inputs
= brw_count_bits(brw
->vs
.prog_data
->outputs_written
);
38 /* BRW_NEW_FRAGMENT_PROGRAM */
39 uint32_t num_outputs
= brw_count_bits(brw
->fragment_program
->Base
.InputsRead
);
40 uint32_t dw1
, dw10
, dw11
;
42 int attr
= 0, input_index
= 0;
44 int urb_start
= ctx
->Transform
.ClipPlanesEnabled
? 2 : 1;
46 int two_side_color
= (ctx
->Light
.Enabled
&& ctx
->Light
.Model
.TwoSide
);
47 uint16_t attr_overrides
[FRAG_ATTRIB_MAX
];
49 /* FINISHME: Attribute Swizzle Control Mode? */
51 GEN7_SBE_SWIZZLE_ENABLE
|
52 num_outputs
<< GEN7_SBE_NUM_OUTPUTS_SHIFT
|
53 (num_inputs
+ 1) / 2 << GEN7_SBE_URB_ENTRY_READ_LENGTH_SHIFT
|
54 urb_start
<< GEN7_SBE_URB_ENTRY_READ_OFFSET_SHIFT
;
57 if (ctx
->Point
.SpriteOrigin
== GL_LOWER_LEFT
)
58 dw1
|= GEN6_SF_POINT_SPRITE_LOWERLEFT
;
62 /* _NEW_LIGHT (flat shading) */
64 if (ctx
->Light
.ShadeModel
== GL_FLAT
) {
65 dw11
|= ((brw
->fragment_program
->Base
.InputsRead
& (FRAG_BIT_COL0
| FRAG_BIT_COL1
)) >>
66 ((brw
->fragment_program
->Base
.InputsRead
& FRAG_BIT_WPOS
) ? 0 : 1));
69 /* Create the mapping from the FS inputs we produce to the VS outputs
72 for (; attr
< FRAG_ATTRIB_MAX
; attr
++) {
73 if (!(brw
->fragment_program
->Base
.InputsRead
& BITFIELD64_BIT(attr
)))
76 if (ctx
->Point
.PointSprite
&&
77 attr
>= FRAG_ATTRIB_TEX0
&& attr
<= FRAG_ATTRIB_TEX7
&&
78 ctx
->Point
.CoordReplace
[attr
- FRAG_ATTRIB_TEX0
]) {
79 dw10
|= (1 << input_index
);
82 if (attr
== FRAG_ATTRIB_PNTC
)
83 dw10
|= (1 << input_index
);
85 /* The hardware can only do the overrides on 16 overrides at a
86 * time, and the other up to 16 have to be lined up so that the
87 * input index = the output index. We'll need to do some
88 * tweaking to make sure that's the case.
90 assert(input_index
< 16 || attr
== input_index
);
92 attr_overrides
[input_index
++] = get_attr_override(brw
, attr
,
96 for (; attr
< FRAG_ATTRIB_MAX
; attr
++)
97 attr_overrides
[input_index
++] = 0;
100 OUT_BATCH(_3DSTATE_SBE
<< 16 | (14 - 2));
103 /* Output dwords 2 through 9 */
104 for (i
= 0; i
< 8; i
++) {
105 OUT_BATCH(attr_overrides
[i
* 2] | attr_overrides
[i
* 2 + 1] << 16);
108 OUT_BATCH(dw10
); /* point sprite texcoord bitmask */
109 OUT_BATCH(dw11
); /* constant interp bitmask */
110 OUT_BATCH(0); /* wrapshortest enables 0-7 */
111 OUT_BATCH(0); /* wrapshortest enables 8-15 */
115 const struct brw_tracked_state gen7_sbe_state
= {
117 .mesa
= (_NEW_LIGHT
|
120 .brw
= (BRW_NEW_CONTEXT
|
121 BRW_NEW_FRAGMENT_PROGRAM
),
122 .cache
= CACHE_NEW_VS_PROG
124 .emit
= upload_sbe_state
,
128 upload_sf_state(struct brw_context
*brw
)
130 struct intel_context
*intel
= &brw
->intel
;
131 struct gl_context
*ctx
= &intel
->ctx
;
132 uint32_t dw1
, dw2
, dw3
;
135 bool render_to_fbo
= brw
->intel
.ctx
.DrawBuffer
->Name
!= 0;
137 dw1
= GEN6_SF_STATISTICS_ENABLE
| GEN6_SF_VIEWPORT_TRANSFORM_ENABLE
;
140 dw1
|= (gen7_depth_format(brw
) << GEN7_SF_DEPTH_BUFFER_SURFACE_FORMAT_SHIFT
);
143 if ((ctx
->Polygon
.FrontFace
== GL_CCW
) ^ render_to_fbo
)
144 dw1
|= GEN6_SF_WINDING_CCW
;
146 if (ctx
->Polygon
.OffsetFill
)
147 dw1
|= GEN6_SF_GLOBAL_DEPTH_OFFSET_SOLID
;
149 if (ctx
->Polygon
.OffsetLine
)
150 dw1
|= GEN6_SF_GLOBAL_DEPTH_OFFSET_WIREFRAME
;
152 if (ctx
->Polygon
.OffsetPoint
)
153 dw1
|= GEN6_SF_GLOBAL_DEPTH_OFFSET_POINT
;
155 switch (ctx
->Polygon
.FrontMode
) {
157 dw1
|= GEN6_SF_FRONT_SOLID
;
161 dw1
|= GEN6_SF_FRONT_WIREFRAME
;
165 dw1
|= GEN6_SF_FRONT_POINT
;
173 switch (ctx
->Polygon
.BackMode
) {
175 dw1
|= GEN6_SF_BACK_SOLID
;
179 dw1
|= GEN6_SF_BACK_WIREFRAME
;
183 dw1
|= GEN6_SF_BACK_POINT
;
193 if (ctx
->Polygon
.CullFlag
) {
194 switch (ctx
->Polygon
.CullFaceMode
) {
196 dw2
|= GEN6_SF_CULL_FRONT
;
199 dw2
|= GEN6_SF_CULL_BACK
;
201 case GL_FRONT_AND_BACK
:
202 dw2
|= GEN6_SF_CULL_BOTH
;
209 dw2
|= GEN6_SF_CULL_NONE
;
213 if (ctx
->Scissor
.Enabled
)
214 dw2
|= GEN6_SF_SCISSOR_ENABLE
;
217 dw2
|= U_FIXED(CLAMP(ctx
->Line
.Width
, 0.0, 7.99), 7) <<
218 GEN6_SF_LINE_WIDTH_SHIFT
;
219 if (ctx
->Line
.SmoothFlag
) {
220 dw2
|= GEN6_SF_LINE_AA_ENABLE
;
221 dw2
|= GEN6_SF_LINE_AA_MODE_TRUE
;
222 dw2
|= GEN6_SF_LINE_END_CAP_WIDTH_1_0
;
225 /* FINISHME: Last Pixel Enable? Vertex Sub Pixel Precision Select?
226 * FINISHME: AA Line Distance Mode?
232 if (!(ctx
->VertexProgram
.PointSizeEnabled
|| ctx
->Point
._Attenuated
))
233 dw3
|= GEN6_SF_USE_STATE_POINT_WIDTH
;
235 /* Clamp to ARB_point_parameters user limits */
236 point_size
= CLAMP(ctx
->Point
.Size
, ctx
->Point
.MinSize
, ctx
->Point
.MaxSize
);
238 /* Clamp to the hardware limits and convert to fixed point */
239 dw3
|= U_FIXED(CLAMP(point_size
, 0.125, 255.875), 3);
242 if (ctx
->Light
.ProvokingVertex
!= GL_FIRST_VERTEX_CONVENTION
) {
244 (2 << GEN6_SF_TRI_PROVOKE_SHIFT
) |
245 (2 << GEN6_SF_TRIFAN_PROVOKE_SHIFT
) |
246 (1 << GEN6_SF_LINE_PROVOKE_SHIFT
);
248 dw3
|= (1 << GEN6_SF_TRIFAN_PROVOKE_SHIFT
);
252 OUT_BATCH(_3DSTATE_SF
<< 16 | (7 - 2));
256 OUT_BATCH_F(ctx
->Polygon
.OffsetUnits
* 2); /* constant. copied from gen4 */
257 OUT_BATCH_F(ctx
->Polygon
.OffsetFactor
); /* scale */
258 OUT_BATCH_F(0.0); /* XXX: global depth offset clamp */
262 const struct brw_tracked_state gen7_sf_state
= {
264 .mesa
= (_NEW_LIGHT
|
270 .brw
= (BRW_NEW_CONTEXT
),
271 .cache
= CACHE_NEW_VS_PROG
273 .emit
= upload_sf_state
,