i965/sf: Consolidate common code for setting up gen6-7 attribute overrides.
[mesa.git] / src / mesa / drivers / dri / i965 / gen7_sf_state.c
1 /*
2 * Copyright © 2011 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include "brw_context.h"
25 #include "brw_state.h"
26 #include "brw_defines.h"
27 #include "brw_util.h"
28 #include "main/macros.h"
29 #include "main/fbobject.h"
30 #include "intel_batchbuffer.h"
31
32 static void
33 upload_sbe_state(struct brw_context *brw)
34 {
35 struct gl_context *ctx = &brw->ctx;
36 /* BRW_NEW_FRAGMENT_PROGRAM */
37 uint32_t num_outputs = _mesa_bitcount_64(brw->fragment_program->Base.InputsRead);
38 uint32_t dw1, dw10, dw11;
39 int i;
40 const int urb_entry_read_offset = BRW_SF_URB_ENTRY_READ_OFFSET;
41 uint16_t attr_overrides[VARYING_SLOT_MAX];
42 /* _NEW_BUFFERS */
43 bool render_to_fbo = _mesa_is_user_fbo(ctx->DrawBuffer);
44 uint32_t point_sprite_origin;
45
46 /* FINISHME: Attribute Swizzle Control Mode? */
47 dw1 = GEN7_SBE_SWIZZLE_ENABLE | num_outputs << GEN7_SBE_NUM_OUTPUTS_SHIFT;
48
49 /* _NEW_POINT
50 *
51 * Window coordinates in an FBO are inverted, which means point
52 * sprite origin must be inverted.
53 */
54 if ((ctx->Point.SpriteOrigin == GL_LOWER_LEFT) != render_to_fbo) {
55 point_sprite_origin = GEN6_SF_POINT_SPRITE_LOWERLEFT;
56 } else {
57 point_sprite_origin = GEN6_SF_POINT_SPRITE_UPPERLEFT;
58 }
59 dw1 |= point_sprite_origin;
60
61
62 dw10 = 0;
63 dw11 = 0;
64
65 /* BRW_NEW_VUE_MAP_GEOM_OUT | _NEW_POINT | _NEW_LIGHT | _NEW_PROGRAM */
66 uint32_t urb_entry_read_length;
67 calculate_attr_overrides(brw, attr_overrides, &dw10, &dw11,
68 &urb_entry_read_length);
69 dw1 |= urb_entry_read_length << GEN7_SBE_URB_ENTRY_READ_LENGTH_SHIFT |
70 urb_entry_read_offset << GEN7_SBE_URB_ENTRY_READ_OFFSET_SHIFT;
71
72 BEGIN_BATCH(14);
73 OUT_BATCH(_3DSTATE_SBE << 16 | (14 - 2));
74 OUT_BATCH(dw1);
75
76 /* Output dwords 2 through 9 */
77 for (i = 0; i < 8; i++) {
78 OUT_BATCH(attr_overrides[i * 2] | attr_overrides[i * 2 + 1] << 16);
79 }
80
81 OUT_BATCH(dw10); /* point sprite texcoord bitmask */
82 OUT_BATCH(dw11); /* constant interp bitmask */
83 OUT_BATCH(0); /* wrapshortest enables 0-7 */
84 OUT_BATCH(0); /* wrapshortest enables 8-15 */
85 ADVANCE_BATCH();
86 }
87
88 const struct brw_tracked_state gen7_sbe_state = {
89 .dirty = {
90 .mesa = (_NEW_BUFFERS |
91 _NEW_LIGHT |
92 _NEW_POINT |
93 _NEW_PROGRAM),
94 .brw = (BRW_NEW_CONTEXT |
95 BRW_NEW_FRAGMENT_PROGRAM |
96 BRW_NEW_VUE_MAP_GEOM_OUT)
97 },
98 .emit = upload_sbe_state,
99 };
100
101 static void
102 upload_sf_state(struct brw_context *brw)
103 {
104 struct gl_context *ctx = &brw->ctx;
105 uint32_t dw1, dw2, dw3;
106 float point_size;
107 /* _NEW_BUFFERS */
108 bool render_to_fbo = _mesa_is_user_fbo(ctx->DrawBuffer);
109 bool multisampled_fbo = ctx->DrawBuffer->Visual.samples > 1;
110
111 dw1 = GEN6_SF_STATISTICS_ENABLE |
112 GEN6_SF_VIEWPORT_TRANSFORM_ENABLE;
113
114 /* _NEW_BUFFERS */
115 dw1 |= (brw_depthbuffer_format(brw) << GEN7_SF_DEPTH_BUFFER_SURFACE_FORMAT_SHIFT);
116
117 /* _NEW_POLYGON */
118 if ((ctx->Polygon.FrontFace == GL_CCW) ^ render_to_fbo)
119 dw1 |= GEN6_SF_WINDING_CCW;
120
121 if (ctx->Polygon.OffsetFill)
122 dw1 |= GEN6_SF_GLOBAL_DEPTH_OFFSET_SOLID;
123
124 if (ctx->Polygon.OffsetLine)
125 dw1 |= GEN6_SF_GLOBAL_DEPTH_OFFSET_WIREFRAME;
126
127 if (ctx->Polygon.OffsetPoint)
128 dw1 |= GEN6_SF_GLOBAL_DEPTH_OFFSET_POINT;
129
130 switch (ctx->Polygon.FrontMode) {
131 case GL_FILL:
132 dw1 |= GEN6_SF_FRONT_SOLID;
133 break;
134
135 case GL_LINE:
136 dw1 |= GEN6_SF_FRONT_WIREFRAME;
137 break;
138
139 case GL_POINT:
140 dw1 |= GEN6_SF_FRONT_POINT;
141 break;
142
143 default:
144 assert(0);
145 break;
146 }
147
148 switch (ctx->Polygon.BackMode) {
149 case GL_FILL:
150 dw1 |= GEN6_SF_BACK_SOLID;
151 break;
152
153 case GL_LINE:
154 dw1 |= GEN6_SF_BACK_WIREFRAME;
155 break;
156
157 case GL_POINT:
158 dw1 |= GEN6_SF_BACK_POINT;
159 break;
160
161 default:
162 assert(0);
163 break;
164 }
165
166 dw2 = 0;
167
168 if (ctx->Polygon.CullFlag) {
169 switch (ctx->Polygon.CullFaceMode) {
170 case GL_FRONT:
171 dw2 |= GEN6_SF_CULL_FRONT;
172 break;
173 case GL_BACK:
174 dw2 |= GEN6_SF_CULL_BACK;
175 break;
176 case GL_FRONT_AND_BACK:
177 dw2 |= GEN6_SF_CULL_BOTH;
178 break;
179 default:
180 assert(0);
181 break;
182 }
183 } else {
184 dw2 |= GEN6_SF_CULL_NONE;
185 }
186
187 /* _NEW_SCISSOR */
188 if (ctx->Scissor.Enabled)
189 dw2 |= GEN6_SF_SCISSOR_ENABLE;
190
191 /* _NEW_LINE */
192 {
193 uint32_t line_width_u3_7 = U_FIXED(CLAMP(ctx->Line.Width, 0.0, 7.99), 7);
194 /* TODO: line width of 0 is not allowed when MSAA enabled */
195 if (line_width_u3_7 == 0)
196 line_width_u3_7 = 1;
197 dw2 |= line_width_u3_7 << GEN6_SF_LINE_WIDTH_SHIFT;
198 }
199 if (ctx->Line.SmoothFlag) {
200 dw2 |= GEN6_SF_LINE_AA_ENABLE;
201 dw2 |= GEN6_SF_LINE_END_CAP_WIDTH_1_0;
202 }
203 if (ctx->Line.StippleFlag && brw->is_haswell) {
204 dw2 |= HSW_SF_LINE_STIPPLE_ENABLE;
205 }
206 /* _NEW_MULTISAMPLE */
207 if (multisampled_fbo && ctx->Multisample.Enabled)
208 dw2 |= GEN6_SF_MSRAST_ON_PATTERN;
209
210 /* FINISHME: Last Pixel Enable? Vertex Sub Pixel Precision Select?
211 */
212
213 dw3 = GEN6_SF_LINE_AA_MODE_TRUE;
214
215 /* _NEW_PROGRAM | _NEW_POINT */
216 if (!(ctx->VertexProgram.PointSizeEnabled || ctx->Point._Attenuated))
217 dw3 |= GEN6_SF_USE_STATE_POINT_WIDTH;
218
219 /* Clamp to ARB_point_parameters user limits */
220 point_size = CLAMP(ctx->Point.Size, ctx->Point.MinSize, ctx->Point.MaxSize);
221
222 /* Clamp to the hardware limits and convert to fixed point */
223 dw3 |= U_FIXED(CLAMP(point_size, 0.125, 255.875), 3);
224
225 /* _NEW_LIGHT */
226 if (ctx->Light.ProvokingVertex != GL_FIRST_VERTEX_CONVENTION) {
227 dw3 |=
228 (2 << GEN6_SF_TRI_PROVOKE_SHIFT) |
229 (2 << GEN6_SF_TRIFAN_PROVOKE_SHIFT) |
230 (1 << GEN6_SF_LINE_PROVOKE_SHIFT);
231 } else {
232 dw3 |= (1 << GEN6_SF_TRIFAN_PROVOKE_SHIFT);
233 }
234
235 BEGIN_BATCH(7);
236 OUT_BATCH(_3DSTATE_SF << 16 | (7 - 2));
237 OUT_BATCH(dw1);
238 OUT_BATCH(dw2);
239 OUT_BATCH(dw3);
240 OUT_BATCH_F(ctx->Polygon.OffsetUnits * 2); /* constant. copied from gen4 */
241 OUT_BATCH_F(ctx->Polygon.OffsetFactor); /* scale */
242 OUT_BATCH_F(0.0); /* XXX: global depth offset clamp */
243 ADVANCE_BATCH();
244 }
245
246 const struct brw_tracked_state gen7_sf_state = {
247 .dirty = {
248 .mesa = (_NEW_LIGHT |
249 _NEW_PROGRAM |
250 _NEW_POLYGON |
251 _NEW_LINE |
252 _NEW_SCISSOR |
253 _NEW_BUFFERS |
254 _NEW_POINT |
255 _NEW_MULTISAMPLE),
256 .brw = BRW_NEW_CONTEXT,
257 .cache = CACHE_NEW_VS_PROG
258 },
259 .emit = upload_sf_state,
260 };