src/mesa/drivers/dri/i965/gen7_sf_state.c

   1 /*
   2  * Copyright © 2011 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include "brw_context.h"
  25 #include "brw_state.h"
  26 #include "brw_defines.h"
  27 #include "brw_util.h"
  28 #include "main/macros.h"
  29 #include "intel_batchbuffer.h"
  30
  31 static void
  32 upload_sbe_state(struct brw_context *brw)
  33 {
  34    struct intel_context *intel = &brw->intel;
  35    struct gl_context *ctx = &intel->ctx;
  36    struct brw_vue_map vue_map;
  37    uint32_t urb_entry_read_length;
  38    /* CACHE_NEW_VS_PROG */
  39    GLbitfield64 vs_outputs_written = brw->vs.prog_data->outputs_written;
  40    /* BRW_NEW_FRAGMENT_PROGRAM */
  41    uint32_t num_outputs = brw_count_bits(brw->fragment_program->Base.InputsRead);
  42    uint32_t dw1, dw10, dw11;
  43    int i;
  44    int attr = 0, input_index = 0;
  45    /* _NEW_TRANSFORM */
  46    int urb_entry_read_offset = ctx->Transform.ClipPlanesEnabled ? 2 : 1;
  47    int nr_userclip = brw_count_bits(ctx->Transform.ClipPlanesEnabled);
  48
  49    /* _NEW_LIGHT */
  50    int two_side_color = (ctx->Light.Enabled && ctx->Light.Model.TwoSide);
  51    uint16_t attr_overrides[FRAG_ATTRIB_MAX];
  52
  53    brw_compute_vue_map(&vue_map, intel, nr_userclip, two_side_color,
  54                        vs_outputs_written);
  55    urb_entry_read_length = (vue_map.num_slots + 1)/2 - urb_entry_read_offset;
  56    if (urb_entry_read_length == 0) {
  57       /* Setting the URB entry read length to 0 causes undefined behavior, so
  58        * if we have no URB data to read, set it to 1.
  59        */
  60       urb_entry_read_length = 1;
  61    }
  62
  63    /* FINISHME: Attribute Swizzle Control Mode? */
  64    dw1 =
  65       GEN7_SBE_SWIZZLE_ENABLE |
  66       num_outputs << GEN7_SBE_NUM_OUTPUTS_SHIFT |
  67       urb_entry_read_length << GEN7_SBE_URB_ENTRY_READ_LENGTH_SHIFT |
  68       urb_entry_read_offset << GEN7_SBE_URB_ENTRY_READ_OFFSET_SHIFT;
  69
  70    /* _NEW_POINT */
  71    if (ctx->Point.SpriteOrigin == GL_LOWER_LEFT)
  72       dw1 |= GEN6_SF_POINT_SPRITE_LOWERLEFT;
  73
  74    dw10 = 0;
  75
  76    /* _NEW_LIGHT (flat shading) */
  77    dw11 = 0;
  78    if (ctx->Light.ShadeModel == GL_FLAT) {
  79        dw11 |= ((brw->fragment_program->Base.InputsRead & (FRAG_BIT_COL0 | FRAG_BIT_COL1)) >>
  80                 ((brw->fragment_program->Base.InputsRead & FRAG_BIT_WPOS) ? 0 : 1));
  81    }
  82
  83    /* Create the mapping from the FS inputs we produce to the VS outputs
  84     * they source from.
  85     */
  86    for (; attr < FRAG_ATTRIB_MAX; attr++) {
  87       if (!(brw->fragment_program->Base.InputsRead & BITFIELD64_BIT(attr)))
  88          continue;
  89
  90       if (ctx->Point.PointSprite &&
  91           attr >= FRAG_ATTRIB_TEX0 && attr <= FRAG_ATTRIB_TEX7 &&
  92           ctx->Point.CoordReplace[attr - FRAG_ATTRIB_TEX0]) {
  93          dw10 |= (1 << input_index);
  94       }
  95
  96       if (attr == FRAG_ATTRIB_PNTC)
  97          dw10 |= (1 << input_index);
  98
  99       /* The hardware can only do the overrides on 16 overrides at a
 100        * time, and the other up to 16 have to be lined up so that the
 101        * input index = the output index.  We'll need to do some
 102        * tweaking to make sure that's the case.
 103        */
 104       assert(input_index < 16 || attr == input_index);
 105
 106       attr_overrides[input_index++] =
 107          get_attr_override(&vue_map, urb_entry_read_offset, attr,
 108                            two_side_color);
 109    }
 110
 111    for (; attr < FRAG_ATTRIB_MAX; attr++)
 112       attr_overrides[input_index++] = 0;
 113
 114    BEGIN_BATCH(14);
 115    OUT_BATCH(_3DSTATE_SBE << 16 | (14 - 2));
 116    OUT_BATCH(dw1);
 117
 118    /* Output dwords 2 through 9 */
 119    for (i = 0; i < 8; i++) {
 120       OUT_BATCH(attr_overrides[i * 2] | attr_overrides[i * 2 + 1] << 16);
 121    }
 122
 123    OUT_BATCH(dw10); /* point sprite texcoord bitmask */
 124    OUT_BATCH(dw11); /* constant interp bitmask */
 125    OUT_BATCH(0); /* wrapshortest enables 0-7 */
 126    OUT_BATCH(0); /* wrapshortest enables 8-15 */
 127    ADVANCE_BATCH();
 128 }
 129
 130 const struct brw_tracked_state gen7_sbe_state = {
 131    .dirty = {
 132       .mesa  = (_NEW_LIGHT |
 133                 _NEW_POINT |
 134                 _NEW_TRANSFORM),
 135       .brw   = (BRW_NEW_CONTEXT |
 136                 BRW_NEW_FRAGMENT_PROGRAM),
 137       .cache = CACHE_NEW_VS_PROG
 138    },
 139    .emit = upload_sbe_state,
 140 };
 141
 142 static void
 143 upload_sf_state(struct brw_context *brw)
 144 {
 145    struct intel_context *intel = &brw->intel;
 146    struct gl_context *ctx = &intel->ctx;
 147    uint32_t dw1, dw2, dw3;
 148    float point_size;
 149    /* _NEW_BUFFERS */
 150    bool render_to_fbo = brw->intel.ctx.DrawBuffer->Name != 0;
 151
 152    dw1 = GEN6_SF_STATISTICS_ENABLE | GEN6_SF_VIEWPORT_TRANSFORM_ENABLE;
 153
 154    /* _NEW_BUFFERS */
 155    dw1 |= (gen7_depth_format(brw) << GEN7_SF_DEPTH_BUFFER_SURFACE_FORMAT_SHIFT);
 156
 157    /* _NEW_POLYGON */
 158    if ((ctx->Polygon.FrontFace == GL_CCW) ^ render_to_fbo)
 159       dw1 |= GEN6_SF_WINDING_CCW;
 160
 161    if (ctx->Polygon.OffsetFill)
 162        dw1 |= GEN6_SF_GLOBAL_DEPTH_OFFSET_SOLID;
 163
 164    if (ctx->Polygon.OffsetLine)
 165        dw1 |= GEN6_SF_GLOBAL_DEPTH_OFFSET_WIREFRAME;
 166
 167    if (ctx->Polygon.OffsetPoint)
 168        dw1 |= GEN6_SF_GLOBAL_DEPTH_OFFSET_POINT;
 169
 170    switch (ctx->Polygon.FrontMode) {
 171    case GL_FILL:
 172        dw1 |= GEN6_SF_FRONT_SOLID;
 173        break;
 174
 175    case GL_LINE:
 176        dw1 |= GEN6_SF_FRONT_WIREFRAME;
 177        break;
 178
 179    case GL_POINT:
 180        dw1 |= GEN6_SF_FRONT_POINT;
 181        break;
 182
 183    default:
 184        assert(0);
 185        break;
 186    }
 187
 188    switch (ctx->Polygon.BackMode) {
 189    case GL_FILL:
 190        dw1 |= GEN6_SF_BACK_SOLID;
 191        break;
 192
 193    case GL_LINE:
 194        dw1 |= GEN6_SF_BACK_WIREFRAME;
 195        break;
 196
 197    case GL_POINT:
 198        dw1 |= GEN6_SF_BACK_POINT;
 199        break;
 200
 201    default:
 202        assert(0);
 203        break;
 204    }
 205
 206    dw2 = 0;
 207
 208    if (ctx->Polygon.CullFlag) {
 209       switch (ctx->Polygon.CullFaceMode) {
 210       case GL_FRONT:
 211          dw2 |= GEN6_SF_CULL_FRONT;
 212          break;
 213       case GL_BACK:
 214          dw2 |= GEN6_SF_CULL_BACK;
 215          break;
 216       case GL_FRONT_AND_BACK:
 217          dw2 |= GEN6_SF_CULL_BOTH;
 218          break;
 219       default:
 220          assert(0);
 221          break;
 222       }
 223    } else {
 224       dw2 |= GEN6_SF_CULL_NONE;
 225    }
 226
 227    /* _NEW_SCISSOR */
 228    if (ctx->Scissor.Enabled)
 229       dw2 |= GEN6_SF_SCISSOR_ENABLE;
 230
 231    /* _NEW_LINE */
 232    dw2 |= U_FIXED(CLAMP(ctx->Line.Width, 0.0, 7.99), 7) <<
 233       GEN6_SF_LINE_WIDTH_SHIFT;
 234    if (ctx->Line.SmoothFlag) {
 235       dw2 |= GEN6_SF_LINE_AA_ENABLE;
 236       dw2 |= GEN6_SF_LINE_AA_MODE_TRUE;
 237       dw2 |= GEN6_SF_LINE_END_CAP_WIDTH_1_0;
 238    }
 239
 240    /* FINISHME: Last Pixel Enable?  Vertex Sub Pixel Precision Select?
 241     * FINISHME: AA Line Distance Mode?
 242     */
 243
 244    dw3 = 0;
 245
 246    /* _NEW_POINT */
 247    if (!(ctx->VertexProgram.PointSizeEnabled || ctx->Point._Attenuated))
 248       dw3 |= GEN6_SF_USE_STATE_POINT_WIDTH;
 249
 250    /* Clamp to ARB_point_parameters user limits */
 251    point_size = CLAMP(ctx->Point.Size, ctx->Point.MinSize, ctx->Point.MaxSize);
 252
 253    /* Clamp to the hardware limits and convert to fixed point */
 254    dw3 |= U_FIXED(CLAMP(point_size, 0.125, 255.875), 3);
 255
 256    /* _NEW_LIGHT */
 257    if (ctx->Light.ProvokingVertex != GL_FIRST_VERTEX_CONVENTION) {
 258       dw3 |=
 259          (2 << GEN6_SF_TRI_PROVOKE_SHIFT) |
 260          (2 << GEN6_SF_TRIFAN_PROVOKE_SHIFT) |
 261          (1 << GEN6_SF_LINE_PROVOKE_SHIFT);
 262    } else {
 263       dw3 |= (1 << GEN6_SF_TRIFAN_PROVOKE_SHIFT);
 264    }
 265
 266    BEGIN_BATCH(7);
 267    OUT_BATCH(_3DSTATE_SF << 16 | (7 - 2));
 268    OUT_BATCH(dw1);
 269    OUT_BATCH(dw2);
 270    OUT_BATCH(dw3);
 271    OUT_BATCH_F(ctx->Polygon.OffsetUnits * 2); /* constant.  copied from gen4 */
 272    OUT_BATCH_F(ctx->Polygon.OffsetFactor); /* scale */
 273    OUT_BATCH_F(0.0); /* XXX: global depth offset clamp */
 274    ADVANCE_BATCH();
 275 }
 276
 277 const struct brw_tracked_state gen7_sf_state = {
 278    .dirty = {
 279       .mesa  = (_NEW_LIGHT |
 280                 _NEW_POLYGON |
 281                 _NEW_LINE |
 282                 _NEW_SCISSOR |
 283                 _NEW_BUFFERS |
 284                 _NEW_POINT),
 285       .brw   = (BRW_NEW_CONTEXT),
 286       .cache = CACHE_NEW_VS_PROG
 287    },
 288    .emit = upload_sf_state,
 289 };