src/mesa/drivers/dri/i965/gen7_sf_state.c

   1 /*
   2  * Copyright © 2011 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include "brw_context.h"
  25 #include "brw_state.h"
  26 #include "brw_defines.h"
  27 #include "brw_util.h"
  28 #include "main/macros.h"
  29 #include "intel_batchbuffer.h"
  30
  31 static void
  32 upload_sbe_state(struct brw_context *brw)
  33 {
  34    struct intel_context *intel = &brw->intel;
  35    struct gl_context *ctx = &intel->ctx;
  36    struct brw_vue_map vue_map;
  37    uint32_t urb_entry_read_length;
  38    /* CACHE_NEW_VS_PROG */
  39    GLbitfield64 vs_outputs_written = brw->vs.prog_data->outputs_written;
  40    /* BRW_NEW_FRAGMENT_PROGRAM */
  41    uint32_t num_outputs = _mesa_bitcount_64(brw->fragment_program->Base.InputsRead);
  42    /* _NEW_LIGHT */
  43    bool shade_model_flat = ctx->Light.ShadeModel == GL_FLAT;
  44    uint32_t dw1, dw10, dw11;
  45    int i;
  46    int attr = 0, input_index = 0;
  47    /* _NEW_TRANSFORM */
  48    int urb_entry_read_offset = 1;
  49    bool userclip_active = (ctx->Transform.ClipPlanesEnabled != 0);
  50    uint16_t attr_overrides[FRAG_ATTRIB_MAX];
  51
  52    brw_compute_vue_map(&vue_map, intel, userclip_active, vs_outputs_written);
  53    urb_entry_read_length = (vue_map.num_slots + 1)/2 - urb_entry_read_offset;
  54    if (urb_entry_read_length == 0) {
  55       /* Setting the URB entry read length to 0 causes undefined behavior, so
  56        * if we have no URB data to read, set it to 1.
  57        */
  58       urb_entry_read_length = 1;
  59    }
  60
  61    /* FINISHME: Attribute Swizzle Control Mode? */
  62    dw1 =
  63       GEN7_SBE_SWIZZLE_ENABLE |
  64       num_outputs << GEN7_SBE_NUM_OUTPUTS_SHIFT |
  65       urb_entry_read_length << GEN7_SBE_URB_ENTRY_READ_LENGTH_SHIFT |
  66       urb_entry_read_offset << GEN7_SBE_URB_ENTRY_READ_OFFSET_SHIFT;
  67
  68    /* _NEW_POINT */
  69    if (ctx->Point.SpriteOrigin == GL_LOWER_LEFT)
  70       dw1 |= GEN6_SF_POINT_SPRITE_LOWERLEFT;
  71
  72    dw10 = 0;
  73    dw11 = 0;
  74
  75    /* Create the mapping from the FS inputs we produce to the VS outputs
  76     * they source from.
  77     */
  78    for (; attr < FRAG_ATTRIB_MAX; attr++) {
  79       enum glsl_interp_qualifier interp_qualifier =
  80          brw->fragment_program->InterpQualifier[attr];
  81       bool is_gl_Color = attr == FRAG_ATTRIB_COL0 || attr == FRAG_ATTRIB_COL1;
  82
  83       if (!(brw->fragment_program->Base.InputsRead & BITFIELD64_BIT(attr)))
  84          continue;
  85
  86       if (ctx->Point.PointSprite &&
  87           attr >= FRAG_ATTRIB_TEX0 && attr <= FRAG_ATTRIB_TEX7 &&
  88           ctx->Point.CoordReplace[attr - FRAG_ATTRIB_TEX0]) {
  89          dw10 |= (1 << input_index);
  90       }
  91
  92       if (attr == FRAG_ATTRIB_PNTC)
  93          dw10 |= (1 << input_index);
  94
  95       /* flat shading */
  96       if (interp_qualifier == INTERP_QUALIFIER_FLAT ||
  97           (shade_model_flat && is_gl_Color &&
  98            interp_qualifier == INTERP_QUALIFIER_NONE))
  99          dw11 |= (1 << input_index);
 100
 101       /* The hardware can only do the overrides on 16 overrides at a
 102        * time, and the other up to 16 have to be lined up so that the
 103        * input index = the output index.  We'll need to do some
 104        * tweaking to make sure that's the case.
 105        */
 106       assert(input_index < 16 || attr == input_index);
 107
 108       attr_overrides[input_index++] =
 109          get_attr_override(&vue_map, urb_entry_read_offset, attr,
 110                            ctx->VertexProgram._TwoSideEnabled);
 111    }
 112
 113    for (; attr < FRAG_ATTRIB_MAX; attr++)
 114       attr_overrides[input_index++] = 0;
 115
 116    BEGIN_BATCH(14);
 117    OUT_BATCH(_3DSTATE_SBE << 16 | (14 - 2));
 118    OUT_BATCH(dw1);
 119
 120    /* Output dwords 2 through 9 */
 121    for (i = 0; i < 8; i++) {
 122       OUT_BATCH(attr_overrides[i * 2] | attr_overrides[i * 2 + 1] << 16);
 123    }
 124
 125    OUT_BATCH(dw10); /* point sprite texcoord bitmask */
 126    OUT_BATCH(dw11); /* constant interp bitmask */
 127    OUT_BATCH(0); /* wrapshortest enables 0-7 */
 128    OUT_BATCH(0); /* wrapshortest enables 8-15 */
 129    ADVANCE_BATCH();
 130 }
 131
 132 const struct brw_tracked_state gen7_sbe_state = {
 133    .dirty = {
 134       .mesa  = (_NEW_LIGHT |
 135                 _NEW_POINT |
 136                 _NEW_TRANSFORM),
 137       .brw   = (BRW_NEW_CONTEXT |
 138                 BRW_NEW_FRAGMENT_PROGRAM),
 139       .cache = CACHE_NEW_VS_PROG
 140    },
 141    .emit = upload_sbe_state,
 142 };
 143
 144 static void
 145 upload_sf_state(struct brw_context *brw)
 146 {
 147    struct intel_context *intel = &brw->intel;
 148    struct gl_context *ctx = &intel->ctx;
 149    uint32_t dw1, dw2, dw3;
 150    float point_size;
 151    /* _NEW_BUFFERS */
 152    bool render_to_fbo = brw->intel.ctx.DrawBuffer->Name != 0;
 153
 154    dw1 = GEN6_SF_STATISTICS_ENABLE | GEN6_SF_VIEWPORT_TRANSFORM_ENABLE;
 155
 156    /* _NEW_BUFFERS */
 157    dw1 |= (brw_depthbuffer_format(brw) << GEN7_SF_DEPTH_BUFFER_SURFACE_FORMAT_SHIFT);
 158
 159    /* _NEW_POLYGON */
 160    if ((ctx->Polygon.FrontFace == GL_CCW) ^ render_to_fbo)
 161       dw1 |= GEN6_SF_WINDING_CCW;
 162
 163    if (ctx->Polygon.OffsetFill)
 164        dw1 |= GEN6_SF_GLOBAL_DEPTH_OFFSET_SOLID;
 165
 166    if (ctx->Polygon.OffsetLine)
 167        dw1 |= GEN6_SF_GLOBAL_DEPTH_OFFSET_WIREFRAME;
 168
 169    if (ctx->Polygon.OffsetPoint)
 170        dw1 |= GEN6_SF_GLOBAL_DEPTH_OFFSET_POINT;
 171
 172    switch (ctx->Polygon.FrontMode) {
 173    case GL_FILL:
 174        dw1 |= GEN6_SF_FRONT_SOLID;
 175        break;
 176
 177    case GL_LINE:
 178        dw1 |= GEN6_SF_FRONT_WIREFRAME;
 179        break;
 180
 181    case GL_POINT:
 182        dw1 |= GEN6_SF_FRONT_POINT;
 183        break;
 184
 185    default:
 186        assert(0);
 187        break;
 188    }
 189
 190    switch (ctx->Polygon.BackMode) {
 191    case GL_FILL:
 192        dw1 |= GEN6_SF_BACK_SOLID;
 193        break;
 194
 195    case GL_LINE:
 196        dw1 |= GEN6_SF_BACK_WIREFRAME;
 197        break;
 198
 199    case GL_POINT:
 200        dw1 |= GEN6_SF_BACK_POINT;
 201        break;
 202
 203    default:
 204        assert(0);
 205        break;
 206    }
 207
 208    dw2 = 0;
 209
 210    if (ctx->Polygon.CullFlag) {
 211       switch (ctx->Polygon.CullFaceMode) {
 212       case GL_FRONT:
 213          dw2 |= GEN6_SF_CULL_FRONT;
 214          break;
 215       case GL_BACK:
 216          dw2 |= GEN6_SF_CULL_BACK;
 217          break;
 218       case GL_FRONT_AND_BACK:
 219          dw2 |= GEN6_SF_CULL_BOTH;
 220          break;
 221       default:
 222          assert(0);
 223          break;
 224       }
 225    } else {
 226       dw2 |= GEN6_SF_CULL_NONE;
 227    }
 228
 229    /* _NEW_SCISSOR */
 230    if (ctx->Scissor.Enabled)
 231       dw2 |= GEN6_SF_SCISSOR_ENABLE;
 232
 233    /* _NEW_LINE */
 234    dw2 |= U_FIXED(CLAMP(ctx->Line.Width, 0.0, 7.99), 7) <<
 235       GEN6_SF_LINE_WIDTH_SHIFT;
 236    if (ctx->Line.SmoothFlag) {
 237       dw2 |= GEN6_SF_LINE_AA_ENABLE;
 238       dw2 |= GEN6_SF_LINE_AA_MODE_TRUE;
 239       dw2 |= GEN6_SF_LINE_END_CAP_WIDTH_1_0;
 240    }
 241
 242    /* FINISHME: Last Pixel Enable?  Vertex Sub Pixel Precision Select?
 243     * FINISHME: AA Line Distance Mode?
 244     */
 245
 246    dw3 = 0;
 247
 248    /* _NEW_POINT */
 249    if (!(ctx->VertexProgram.PointSizeEnabled || ctx->Point._Attenuated))
 250       dw3 |= GEN6_SF_USE_STATE_POINT_WIDTH;
 251
 252    /* Clamp to ARB_point_parameters user limits */
 253    point_size = CLAMP(ctx->Point.Size, ctx->Point.MinSize, ctx->Point.MaxSize);
 254
 255    /* Clamp to the hardware limits and convert to fixed point */
 256    dw3 |= U_FIXED(CLAMP(point_size, 0.125, 255.875), 3);
 257
 258    /* _NEW_LIGHT */
 259    if (ctx->Light.ProvokingVertex != GL_FIRST_VERTEX_CONVENTION) {
 260       dw3 |=
 261          (2 << GEN6_SF_TRI_PROVOKE_SHIFT) |
 262          (2 << GEN6_SF_TRIFAN_PROVOKE_SHIFT) |
 263          (1 << GEN6_SF_LINE_PROVOKE_SHIFT);
 264    } else {
 265       dw3 |= (1 << GEN6_SF_TRIFAN_PROVOKE_SHIFT);
 266    }
 267
 268    BEGIN_BATCH(7);
 269    OUT_BATCH(_3DSTATE_SF << 16 | (7 - 2));
 270    OUT_BATCH(dw1);
 271    OUT_BATCH(dw2);
 272    OUT_BATCH(dw3);
 273    OUT_BATCH_F(ctx->Polygon.OffsetUnits * 2); /* constant.  copied from gen4 */
 274    OUT_BATCH_F(ctx->Polygon.OffsetFactor); /* scale */
 275    OUT_BATCH_F(0.0); /* XXX: global depth offset clamp */
 276    ADVANCE_BATCH();
 277 }
 278
 279 const struct brw_tracked_state gen7_sf_state = {
 280    .dirty = {
 281       .mesa  = (_NEW_LIGHT |
 282                 _NEW_PROGRAM |
 283                 _NEW_POLYGON |
 284                 _NEW_LINE |
 285                 _NEW_SCISSOR |
 286                 _NEW_BUFFERS |
 287                 _NEW_POINT),
 288       .brw   = (BRW_NEW_CONTEXT),
 289       .cache = CACHE_NEW_VS_PROG
 290    },
 291    .emit = upload_sf_state,
 292 };