src/mesa/drivers/dri/i965/gen7_sf_state.c

   1 /*
   2  * Copyright © 2011 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include "brw_context.h"
  25 #include "brw_state.h"
  26 #include "brw_defines.h"
  27 #include "brw_util.h"
  28 #include "main/macros.h"
  29 #include "main/fbobject.h"
  30 #include "intel_batchbuffer.h"
  31
  32 static void
  33 upload_sbe_state(struct brw_context *brw)
  34 {
  35    struct intel_context *intel = &brw->intel;
  36    struct gl_context *ctx = &intel->ctx;
  37    uint32_t urb_entry_read_length;
  38    /* BRW_NEW_FRAGMENT_PROGRAM */
  39    uint32_t num_outputs = _mesa_bitcount_64(brw->fragment_program->Base.InputsRead);
  40    /* _NEW_LIGHT */
  41    bool shade_model_flat = ctx->Light.ShadeModel == GL_FLAT;
  42    uint32_t dw1, dw10, dw11;
  43    int i;
  44    int attr = 0, input_index = 0;
  45    int urb_entry_read_offset = 1;
  46    uint16_t attr_overrides[FRAG_ATTRIB_MAX];
  47    /* _NEW_BUFFERS */
  48    bool render_to_fbo = _mesa_is_user_fbo(ctx->DrawBuffer);
  49    uint32_t point_sprite_origin;
  50
  51    /* CACHE_NEW_VS_PROG */
  52    urb_entry_read_length = ((brw->vs.prog_data->vue_map.num_slots + 1) / 2 -
  53                             urb_entry_read_offset);
  54    if (urb_entry_read_length == 0) {
  55       /* Setting the URB entry read length to 0 causes undefined behavior, so
  56        * if we have no URB data to read, set it to 1.
  57        */
  58       urb_entry_read_length = 1;
  59    }
  60
  61    /* FINISHME: Attribute Swizzle Control Mode? */
  62    dw1 =
  63       GEN7_SBE_SWIZZLE_ENABLE |
  64       num_outputs << GEN7_SBE_NUM_OUTPUTS_SHIFT |
  65       urb_entry_read_length << GEN7_SBE_URB_ENTRY_READ_LENGTH_SHIFT |
  66       urb_entry_read_offset << GEN7_SBE_URB_ENTRY_READ_OFFSET_SHIFT;
  67
  68    /* _NEW_POINT
  69     *
  70     * Window coordinates in an FBO are inverted, which means point
  71     * sprite origin must be inverted.
  72     */
  73    if ((ctx->Point.SpriteOrigin == GL_LOWER_LEFT) != render_to_fbo) {
  74       point_sprite_origin = GEN6_SF_POINT_SPRITE_LOWERLEFT;
  75    } else {
  76       point_sprite_origin = GEN6_SF_POINT_SPRITE_UPPERLEFT;
  77    }
  78    dw1 |= point_sprite_origin;
  79
  80
  81    dw10 = 0;
  82    dw11 = 0;
  83
  84    /* Create the mapping from the FS inputs we produce to the VS outputs
  85     * they source from.
  86     */
  87    for (; attr < FRAG_ATTRIB_MAX; attr++) {
  88       enum glsl_interp_qualifier interp_qualifier =
  89          brw->fragment_program->InterpQualifier[attr];
  90       bool is_gl_Color = attr == FRAG_ATTRIB_COL0 || attr == FRAG_ATTRIB_COL1;
  91
  92       if (!(brw->fragment_program->Base.InputsRead & BITFIELD64_BIT(attr)))
  93          continue;
  94
  95       if (ctx->Point.PointSprite &&
  96           attr >= FRAG_ATTRIB_TEX0 && attr <= FRAG_ATTRIB_TEX7 &&
  97           ctx->Point.CoordReplace[attr - FRAG_ATTRIB_TEX0]) {
  98          dw10 |= (1 << input_index);
  99       }
 100
 101       if (attr == FRAG_ATTRIB_PNTC)
 102          dw10 |= (1 << input_index);
 103
 104       /* flat shading */
 105       if (interp_qualifier == INTERP_QUALIFIER_FLAT ||
 106           (shade_model_flat && is_gl_Color &&
 107            interp_qualifier == INTERP_QUALIFIER_NONE))
 108          dw11 |= (1 << input_index);
 109
 110       /* The hardware can only do the overrides on 16 overrides at a
 111        * time, and the other up to 16 have to be lined up so that the
 112        * input index = the output index.  We'll need to do some
 113        * tweaking to make sure that's the case.
 114        */
 115       assert(input_index < 16 || attr == input_index);
 116
 117       /* CACHE_NEW_VS_PROG | _NEW_LIGHT | _NEW_PROGRAM */
 118       attr_overrides[input_index++] =
 119          get_attr_override(&brw->vs.prog_data->vue_map,
 120                            urb_entry_read_offset, attr,
 121                            ctx->VertexProgram._TwoSideEnabled);
 122    }
 123
 124    for (; input_index < FRAG_ATTRIB_MAX; input_index++)
 125       attr_overrides[input_index] = 0;
 126
 127    BEGIN_BATCH(14);
 128    OUT_BATCH(_3DSTATE_SBE << 16 | (14 - 2));
 129    OUT_BATCH(dw1);
 130
 131    /* Output dwords 2 through 9 */
 132    for (i = 0; i < 8; i++) {
 133       OUT_BATCH(attr_overrides[i * 2] | attr_overrides[i * 2 + 1] << 16);
 134    }
 135
 136    OUT_BATCH(dw10); /* point sprite texcoord bitmask */
 137    OUT_BATCH(dw11); /* constant interp bitmask */
 138    OUT_BATCH(0); /* wrapshortest enables 0-7 */
 139    OUT_BATCH(0); /* wrapshortest enables 8-15 */
 140    ADVANCE_BATCH();
 141 }
 142
 143 const struct brw_tracked_state gen7_sbe_state = {
 144    .dirty = {
 145       .mesa  = (_NEW_LIGHT |
 146                 _NEW_POINT |
 147                 _NEW_PROGRAM),
 148       .brw   = (BRW_NEW_CONTEXT |
 149                 BRW_NEW_FRAGMENT_PROGRAM),
 150       .cache = CACHE_NEW_VS_PROG
 151    },
 152    .emit = upload_sbe_state,
 153 };
 154
 155 static void
 156 upload_sf_state(struct brw_context *brw)
 157 {
 158    struct intel_context *intel = &brw->intel;
 159    struct gl_context *ctx = &intel->ctx;
 160    uint32_t dw1, dw2, dw3;
 161    float point_size;
 162    /* _NEW_BUFFERS */
 163    bool render_to_fbo = _mesa_is_user_fbo(brw->intel.ctx.DrawBuffer);
 164    bool multisampled_fbo = false;
 165    if (ctx->DrawBuffer->_ColorDrawBuffers[0])
 166       multisampled_fbo = ctx->DrawBuffer->_ColorDrawBuffers[0]->NumSamples > 0;
 167
 168    dw1 = GEN6_SF_STATISTICS_ENABLE |
 169          GEN6_SF_VIEWPORT_TRANSFORM_ENABLE;
 170
 171    /* _NEW_BUFFERS */
 172    dw1 |= (brw_depthbuffer_format(brw) << GEN7_SF_DEPTH_BUFFER_SURFACE_FORMAT_SHIFT);
 173
 174    /* _NEW_POLYGON */
 175    if ((ctx->Polygon.FrontFace == GL_CCW) ^ render_to_fbo)
 176       dw1 |= GEN6_SF_WINDING_CCW;
 177
 178    if (ctx->Polygon.OffsetFill)
 179        dw1 |= GEN6_SF_GLOBAL_DEPTH_OFFSET_SOLID;
 180
 181    if (ctx->Polygon.OffsetLine)
 182        dw1 |= GEN6_SF_GLOBAL_DEPTH_OFFSET_WIREFRAME;
 183
 184    if (ctx->Polygon.OffsetPoint)
 185        dw1 |= GEN6_SF_GLOBAL_DEPTH_OFFSET_POINT;
 186
 187    switch (ctx->Polygon.FrontMode) {
 188    case GL_FILL:
 189        dw1 |= GEN6_SF_FRONT_SOLID;
 190        break;
 191
 192    case GL_LINE:
 193        dw1 |= GEN6_SF_FRONT_WIREFRAME;
 194        break;
 195
 196    case GL_POINT:
 197        dw1 |= GEN6_SF_FRONT_POINT;
 198        break;
 199
 200    default:
 201        assert(0);
 202        break;
 203    }
 204
 205    switch (ctx->Polygon.BackMode) {
 206    case GL_FILL:
 207        dw1 |= GEN6_SF_BACK_SOLID;
 208        break;
 209
 210    case GL_LINE:
 211        dw1 |= GEN6_SF_BACK_WIREFRAME;
 212        break;
 213
 214    case GL_POINT:
 215        dw1 |= GEN6_SF_BACK_POINT;
 216        break;
 217
 218    default:
 219        assert(0);
 220        break;
 221    }
 222
 223    dw2 = 0;
 224
 225    if (ctx->Polygon.CullFlag) {
 226       switch (ctx->Polygon.CullFaceMode) {
 227       case GL_FRONT:
 228          dw2 |= GEN6_SF_CULL_FRONT;
 229          break;
 230       case GL_BACK:
 231          dw2 |= GEN6_SF_CULL_BACK;
 232          break;
 233       case GL_FRONT_AND_BACK:
 234          dw2 |= GEN6_SF_CULL_BOTH;
 235          break;
 236       default:
 237          assert(0);
 238          break;
 239       }
 240    } else {
 241       dw2 |= GEN6_SF_CULL_NONE;
 242    }
 243
 244    /* _NEW_SCISSOR */
 245    if (ctx->Scissor.Enabled)
 246       dw2 |= GEN6_SF_SCISSOR_ENABLE;
 247
 248    /* _NEW_LINE */
 249    {
 250       uint32_t line_width_u3_7 = U_FIXED(CLAMP(ctx->Line.Width, 0.0, 7.99), 7);
 251       /* TODO: line width of 0 is not allowed when MSAA enabled */
 252       if (line_width_u3_7 == 0)
 253          line_width_u3_7 = 1;
 254       dw2 |= line_width_u3_7 << GEN6_SF_LINE_WIDTH_SHIFT;
 255    }
 256    if (ctx->Line.SmoothFlag) {
 257       dw2 |= GEN6_SF_LINE_AA_ENABLE;
 258       dw2 |= GEN6_SF_LINE_AA_MODE_TRUE;
 259       dw2 |= GEN6_SF_LINE_END_CAP_WIDTH_1_0;
 260    }
 261    if (ctx->Line.StippleFlag && intel->is_haswell) {
 262       dw2 |= HSW_SF_LINE_STIPPLE_ENABLE;
 263    }
 264    /* _NEW_MULTISAMPLE */
 265    if (multisampled_fbo && ctx->Multisample.Enabled)
 266       dw2 |= GEN6_SF_MSRAST_ON_PATTERN;
 267
 268    /* FINISHME: Last Pixel Enable?  Vertex Sub Pixel Precision Select?
 269     * FINISHME: AA Line Distance Mode?
 270     */
 271
 272    dw3 = 0;
 273
 274    /* _NEW_PROGRAM | _NEW_POINT */
 275    if (!(ctx->VertexProgram.PointSizeEnabled || ctx->Point._Attenuated))
 276       dw3 |= GEN6_SF_USE_STATE_POINT_WIDTH;
 277
 278    /* Clamp to ARB_point_parameters user limits */
 279    point_size = CLAMP(ctx->Point.Size, ctx->Point.MinSize, ctx->Point.MaxSize);
 280
 281    /* Clamp to the hardware limits and convert to fixed point */
 282    dw3 |= U_FIXED(CLAMP(point_size, 0.125, 255.875), 3);
 283
 284    /* _NEW_LIGHT */
 285    if (ctx->Light.ProvokingVertex != GL_FIRST_VERTEX_CONVENTION) {
 286       dw3 |=
 287          (2 << GEN6_SF_TRI_PROVOKE_SHIFT) |
 288          (2 << GEN6_SF_TRIFAN_PROVOKE_SHIFT) |
 289          (1 << GEN6_SF_LINE_PROVOKE_SHIFT);
 290    } else {
 291       dw3 |= (1 << GEN6_SF_TRIFAN_PROVOKE_SHIFT);
 292    }
 293
 294    BEGIN_BATCH(7);
 295    OUT_BATCH(_3DSTATE_SF << 16 | (7 - 2));
 296    OUT_BATCH(dw1);
 297    OUT_BATCH(dw2);
 298    OUT_BATCH(dw3);
 299    OUT_BATCH_F(ctx->Polygon.OffsetUnits * 2); /* constant.  copied from gen4 */
 300    OUT_BATCH_F(ctx->Polygon.OffsetFactor); /* scale */
 301    OUT_BATCH_F(0.0); /* XXX: global depth offset clamp */
 302    ADVANCE_BATCH();
 303 }
 304
 305 const struct brw_tracked_state gen7_sf_state = {
 306    .dirty = {
 307       .mesa  = (_NEW_LIGHT |
 308                 _NEW_PROGRAM |
 309                 _NEW_POLYGON |
 310                 _NEW_LINE |
 311                 _NEW_SCISSOR |
 312                 _NEW_BUFFERS |
 313                 _NEW_POINT |
 314                 _NEW_MULTISAMPLE),
 315       .brw   = BRW_NEW_CONTEXT,
 316       .cache = CACHE_NEW_VS_PROG
 317    },
 318    .emit = upload_sf_state,
 319 };