i965: Move VUE map computation to once at VS compile time.
[mesa.git] / src / mesa / drivers / dri / i965 / gen7_sf_state.c
1 /*
2 * Copyright © 2011 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include "brw_context.h"
25 #include "brw_state.h"
26 #include "brw_defines.h"
27 #include "brw_util.h"
28 #include "main/macros.h"
29 #include "intel_batchbuffer.h"
30
31 static void
32 upload_sbe_state(struct brw_context *brw)
33 {
34 struct intel_context *intel = &brw->intel;
35 struct gl_context *ctx = &intel->ctx;
36 uint32_t urb_entry_read_length;
37 /* BRW_NEW_FRAGMENT_PROGRAM */
38 uint32_t num_outputs = _mesa_bitcount_64(brw->fragment_program->Base.InputsRead);
39 /* _NEW_LIGHT */
40 bool shade_model_flat = ctx->Light.ShadeModel == GL_FLAT;
41 uint32_t dw1, dw10, dw11;
42 int i;
43 int attr = 0, input_index = 0;
44 int urb_entry_read_offset = 1;
45 uint16_t attr_overrides[FRAG_ATTRIB_MAX];
46 /* _NEW_BUFFERS */
47 bool render_to_fbo = ctx->DrawBuffer->Name != 0;
48 uint32_t point_sprite_origin;
49
50 /* CACHE_NEW_VS_PROG */
51 urb_entry_read_length = ((brw->vs.prog_data->vue_map.num_slots + 1) / 2 -
52 urb_entry_read_offset);
53 if (urb_entry_read_length == 0) {
54 /* Setting the URB entry read length to 0 causes undefined behavior, so
55 * if we have no URB data to read, set it to 1.
56 */
57 urb_entry_read_length = 1;
58 }
59
60 /* FINISHME: Attribute Swizzle Control Mode? */
61 dw1 =
62 GEN7_SBE_SWIZZLE_ENABLE |
63 num_outputs << GEN7_SBE_NUM_OUTPUTS_SHIFT |
64 urb_entry_read_length << GEN7_SBE_URB_ENTRY_READ_LENGTH_SHIFT |
65 urb_entry_read_offset << GEN7_SBE_URB_ENTRY_READ_OFFSET_SHIFT;
66
67 /* _NEW_POINT
68 *
69 * Window coordinates in an FBO are inverted, which means point
70 * sprite origin must be inverted.
71 */
72 if ((ctx->Point.SpriteOrigin == GL_LOWER_LEFT) != render_to_fbo) {
73 point_sprite_origin = GEN6_SF_POINT_SPRITE_LOWERLEFT;
74 } else {
75 point_sprite_origin = GEN6_SF_POINT_SPRITE_UPPERLEFT;
76 }
77 dw1 |= point_sprite_origin;
78
79
80 dw10 = 0;
81 dw11 = 0;
82
83 /* Create the mapping from the FS inputs we produce to the VS outputs
84 * they source from.
85 */
86 for (; attr < FRAG_ATTRIB_MAX; attr++) {
87 enum glsl_interp_qualifier interp_qualifier =
88 brw->fragment_program->InterpQualifier[attr];
89 bool is_gl_Color = attr == FRAG_ATTRIB_COL0 || attr == FRAG_ATTRIB_COL1;
90
91 if (!(brw->fragment_program->Base.InputsRead & BITFIELD64_BIT(attr)))
92 continue;
93
94 if (ctx->Point.PointSprite &&
95 attr >= FRAG_ATTRIB_TEX0 && attr <= FRAG_ATTRIB_TEX7 &&
96 ctx->Point.CoordReplace[attr - FRAG_ATTRIB_TEX0]) {
97 dw10 |= (1 << input_index);
98 }
99
100 if (attr == FRAG_ATTRIB_PNTC)
101 dw10 |= (1 << input_index);
102
103 /* flat shading */
104 if (interp_qualifier == INTERP_QUALIFIER_FLAT ||
105 (shade_model_flat && is_gl_Color &&
106 interp_qualifier == INTERP_QUALIFIER_NONE))
107 dw11 |= (1 << input_index);
108
109 /* The hardware can only do the overrides on 16 overrides at a
110 * time, and the other up to 16 have to be lined up so that the
111 * input index = the output index. We'll need to do some
112 * tweaking to make sure that's the case.
113 */
114 assert(input_index < 16 || attr == input_index);
115
116 /* CACHE_NEW_VS_PROG | _NEW_LIGHT | _NEW_PROGRAM */
117 attr_overrides[input_index++] =
118 get_attr_override(&brw->vs.prog_data->vue_map,
119 urb_entry_read_offset, attr,
120 ctx->VertexProgram._TwoSideEnabled);
121 }
122
123 for (; input_index < FRAG_ATTRIB_MAX; input_index++)
124 attr_overrides[input_index] = 0;
125
126 BEGIN_BATCH(14);
127 OUT_BATCH(_3DSTATE_SBE << 16 | (14 - 2));
128 OUT_BATCH(dw1);
129
130 /* Output dwords 2 through 9 */
131 for (i = 0; i < 8; i++) {
132 OUT_BATCH(attr_overrides[i * 2] | attr_overrides[i * 2 + 1] << 16);
133 }
134
135 OUT_BATCH(dw10); /* point sprite texcoord bitmask */
136 OUT_BATCH(dw11); /* constant interp bitmask */
137 OUT_BATCH(0); /* wrapshortest enables 0-7 */
138 OUT_BATCH(0); /* wrapshortest enables 8-15 */
139 ADVANCE_BATCH();
140 }
141
142 const struct brw_tracked_state gen7_sbe_state = {
143 .dirty = {
144 .mesa = (_NEW_LIGHT |
145 _NEW_POINT |
146 _NEW_PROGRAM),
147 .brw = (BRW_NEW_CONTEXT |
148 BRW_NEW_FRAGMENT_PROGRAM),
149 .cache = CACHE_NEW_VS_PROG
150 },
151 .emit = upload_sbe_state,
152 };
153
154 static void
155 upload_sf_state(struct brw_context *brw)
156 {
157 struct intel_context *intel = &brw->intel;
158 struct gl_context *ctx = &intel->ctx;
159 uint32_t dw1, dw2, dw3;
160 float point_size;
161 /* _NEW_BUFFERS */
162 bool render_to_fbo = brw->intel.ctx.DrawBuffer->Name != 0;
163
164 dw1 = GEN6_SF_STATISTICS_ENABLE |
165 GEN6_SF_VIEWPORT_TRANSFORM_ENABLE;
166
167 /* _NEW_BUFFERS */
168 dw1 |= (brw_depthbuffer_format(brw) << GEN7_SF_DEPTH_BUFFER_SURFACE_FORMAT_SHIFT);
169
170 /* _NEW_POLYGON */
171 if ((ctx->Polygon.FrontFace == GL_CCW) ^ render_to_fbo)
172 dw1 |= GEN6_SF_WINDING_CCW;
173
174 if (ctx->Polygon.OffsetFill)
175 dw1 |= GEN6_SF_GLOBAL_DEPTH_OFFSET_SOLID;
176
177 if (ctx->Polygon.OffsetLine)
178 dw1 |= GEN6_SF_GLOBAL_DEPTH_OFFSET_WIREFRAME;
179
180 if (ctx->Polygon.OffsetPoint)
181 dw1 |= GEN6_SF_GLOBAL_DEPTH_OFFSET_POINT;
182
183 switch (ctx->Polygon.FrontMode) {
184 case GL_FILL:
185 dw1 |= GEN6_SF_FRONT_SOLID;
186 break;
187
188 case GL_LINE:
189 dw1 |= GEN6_SF_FRONT_WIREFRAME;
190 break;
191
192 case GL_POINT:
193 dw1 |= GEN6_SF_FRONT_POINT;
194 break;
195
196 default:
197 assert(0);
198 break;
199 }
200
201 switch (ctx->Polygon.BackMode) {
202 case GL_FILL:
203 dw1 |= GEN6_SF_BACK_SOLID;
204 break;
205
206 case GL_LINE:
207 dw1 |= GEN6_SF_BACK_WIREFRAME;
208 break;
209
210 case GL_POINT:
211 dw1 |= GEN6_SF_BACK_POINT;
212 break;
213
214 default:
215 assert(0);
216 break;
217 }
218
219 dw2 = 0;
220
221 if (ctx->Polygon.CullFlag) {
222 switch (ctx->Polygon.CullFaceMode) {
223 case GL_FRONT:
224 dw2 |= GEN6_SF_CULL_FRONT;
225 break;
226 case GL_BACK:
227 dw2 |= GEN6_SF_CULL_BACK;
228 break;
229 case GL_FRONT_AND_BACK:
230 dw2 |= GEN6_SF_CULL_BOTH;
231 break;
232 default:
233 assert(0);
234 break;
235 }
236 } else {
237 dw2 |= GEN6_SF_CULL_NONE;
238 }
239
240 /* _NEW_SCISSOR */
241 if (ctx->Scissor.Enabled)
242 dw2 |= GEN6_SF_SCISSOR_ENABLE;
243
244 /* _NEW_LINE */
245 dw2 |= U_FIXED(CLAMP(ctx->Line.Width, 0.0, 7.99), 7) <<
246 GEN6_SF_LINE_WIDTH_SHIFT;
247 if (ctx->Line.SmoothFlag) {
248 dw2 |= GEN6_SF_LINE_AA_ENABLE;
249 dw2 |= GEN6_SF_LINE_AA_MODE_TRUE;
250 dw2 |= GEN6_SF_LINE_END_CAP_WIDTH_1_0;
251 }
252
253 /* FINISHME: Last Pixel Enable? Vertex Sub Pixel Precision Select?
254 * FINISHME: AA Line Distance Mode?
255 */
256
257 dw3 = 0;
258
259 /* _NEW_PROGRAM | _NEW_POINT */
260 if (!(ctx->VertexProgram.PointSizeEnabled || ctx->Point._Attenuated))
261 dw3 |= GEN6_SF_USE_STATE_POINT_WIDTH;
262
263 /* Clamp to ARB_point_parameters user limits */
264 point_size = CLAMP(ctx->Point.Size, ctx->Point.MinSize, ctx->Point.MaxSize);
265
266 /* Clamp to the hardware limits and convert to fixed point */
267 dw3 |= U_FIXED(CLAMP(point_size, 0.125, 255.875), 3);
268
269 /* _NEW_LIGHT */
270 if (ctx->Light.ProvokingVertex != GL_FIRST_VERTEX_CONVENTION) {
271 dw3 |=
272 (2 << GEN6_SF_TRI_PROVOKE_SHIFT) |
273 (2 << GEN6_SF_TRIFAN_PROVOKE_SHIFT) |
274 (1 << GEN6_SF_LINE_PROVOKE_SHIFT);
275 } else {
276 dw3 |= (1 << GEN6_SF_TRIFAN_PROVOKE_SHIFT);
277 }
278
279 BEGIN_BATCH(7);
280 OUT_BATCH(_3DSTATE_SF << 16 | (7 - 2));
281 OUT_BATCH(dw1);
282 OUT_BATCH(dw2);
283 OUT_BATCH(dw3);
284 OUT_BATCH_F(ctx->Polygon.OffsetUnits * 2); /* constant. copied from gen4 */
285 OUT_BATCH_F(ctx->Polygon.OffsetFactor); /* scale */
286 OUT_BATCH_F(0.0); /* XXX: global depth offset clamp */
287 ADVANCE_BATCH();
288 }
289
290 const struct brw_tracked_state gen7_sf_state = {
291 .dirty = {
292 .mesa = (_NEW_LIGHT |
293 _NEW_PROGRAM |
294 _NEW_POLYGON |
295 _NEW_LINE |
296 _NEW_SCISSOR |
297 _NEW_BUFFERS |
298 _NEW_POINT),
299 .brw = BRW_NEW_CONTEXT,
300 .cache = CACHE_NEW_VS_PROG
301 },
302 .emit = upload_sf_state,
303 };