src/mesa/drivers/dri/i965/gen7_sol_state.c

   1 /*
   2  * Copyright © 2011 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 /**
  25  * @file gen7_sol_state.c
  26  *
  27  * Controls the stream output logic (SOL) stage of the gen7 hardware, which is
  28  * used to implement GL_EXT_transform_feedback.
  29  */
  30
  31 #include "brw_context.h"
  32 #include "brw_state.h"
  33 #include "brw_defines.h"
  34 #include "intel_batchbuffer.h"
  35 #include "intel_buffer_objects.h"
  36
  37 static void
  38 upload_3dstate_so_buffers(struct brw_context *brw)
  39 {
  40    struct intel_context *intel = &brw->intel;
  41    struct gl_context *ctx = &intel->ctx;
  42    /* BRW_NEW_VERTEX_PROGRAM */
  43    const struct gl_shader_program *vs_prog =
  44       ctx->Shader.CurrentVertexProgram;
  45    const struct gl_transform_feedback_info *linked_xfb_info =
  46       &vs_prog->LinkedTransformFeedback;
  47    /* _NEW_TRANSFORM_FEEDBACK */
  48    struct gl_transform_feedback_object *xfb_obj =
  49       ctx->TransformFeedback.CurrentObject;
  50    int i;
  51
  52    /* Set up the up to 4 output buffers.  These are the ranges defined in the
  53     * gl_transform_feedback_object.
  54     */
  55    for (i = 0; i < 4; i++) {
  56       struct gl_buffer_object *bufferobj = xfb_obj->Buffers[i];
  57       drm_intel_bo *bo;
  58       uint32_t start, end;
  59
  60       if (!xfb_obj->Buffers[i]) {
  61          /* The pitch of 0 in this command indicates that the buffer is
  62           * unbound and won't be written to.
  63           */
  64          BEGIN_BATCH(4);
  65          OUT_BATCH(_3DSTATE_SO_BUFFER << 16 | (4 - 2));
  66          OUT_BATCH((i << SO_BUFFER_INDEX_SHIFT));
  67          OUT_BATCH(0);
  68          OUT_BATCH(0);
  69          ADVANCE_BATCH();
  70
  71          continue;
  72       }
  73
  74       bo = intel_buffer_object(bufferobj)->buffer;
  75
  76       start = xfb_obj->Offset[i];
  77       assert(start % 4 == 0);
  78       end = ALIGN(start + xfb_obj->Size[i], 4);
  79       assert(end <= bo->size);
  80
  81       BEGIN_BATCH(4);
  82       OUT_BATCH(_3DSTATE_SO_BUFFER << 16 | (4 - 2));
  83       OUT_BATCH((i << SO_BUFFER_INDEX_SHIFT) |
  84                 ((linked_xfb_info->BufferStride[i] * 4) <<
  85                  SO_BUFFER_PITCH_SHIFT));
  86       OUT_RELOC(bo, I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, start);
  87       OUT_RELOC(bo, I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, end);
  88       ADVANCE_BATCH();
  89    }
  90 }
  91
  92 /**
  93  * Outputs the 3DSTATE_SO_DECL_LIST command.
  94  *
  95  * The data output is a series of 64-bit entries containing a SO_DECL per
  96  * stream.  We only have one stream of rendering coming out of the GS unit, so
  97  * we only emit stream 0 (low 16 bits) SO_DECLs.
  98  */
  99 static void
 100 upload_3dstate_so_decl_list(struct brw_context *brw,
 101                             struct brw_vue_map *vue_map)
 102 {
 103    struct intel_context *intel = &brw->intel;
 104    struct gl_context *ctx = &intel->ctx;
 105    /* BRW_NEW_VERTEX_PROGRAM */
 106    const struct gl_shader_program *vs_prog =
 107       ctx->Shader.CurrentVertexProgram;
 108    /* _NEW_TRANSFORM_FEEDBACK */
 109    const struct gl_transform_feedback_info *linked_xfb_info =
 110       &vs_prog->LinkedTransformFeedback;
 111    int i;
 112    uint16_t so_decl[128];
 113    int buffer_mask = 0;
 114    int next_offset[4] = {0, 0, 0, 0};
 115
 116    STATIC_ASSERT(ARRAY_SIZE(so_decl) >= MAX_PROGRAM_OUTPUTS);
 117
 118    /* Construct the list of SO_DECLs to be emitted.  The formatting of the
 119     * command is feels strange -- each dword pair contains a SO_DECL per stream.
 120     */
 121    for (i = 0; i < linked_xfb_info->NumOutputs; i++) {
 122       int buffer = linked_xfb_info->Outputs[i].OutputBuffer;
 123       uint16_t decl = 0;
 124       int vert_result = linked_xfb_info->Outputs[i].OutputRegister;
 125       unsigned component_mask =
 126          (1 << linked_xfb_info->Outputs[i].NumComponents) - 1;
 127
 128       /* gl_PointSize is stored in VERT_RESULT_PSIZ.w. */
 129       if (vert_result == VERT_RESULT_PSIZ) {
 130          assert(linked_xfb_info->Outputs[i].NumComponents == 1);
 131          component_mask <<= 3;
 132       }
 133
 134       buffer_mask |= 1 << buffer;
 135
 136       decl |= buffer << SO_DECL_OUTPUT_BUFFER_SLOT_SHIFT;
 137       decl |= vue_map->vert_result_to_slot[vert_result] <<
 138          SO_DECL_REGISTER_INDEX_SHIFT;
 139       decl |= component_mask << SO_DECL_COMPONENT_MASK_SHIFT;
 140
 141       /* This assert should be true until GL_ARB_transform_feedback_instanced
 142        * is added and we start using the hole flag.
 143        */
 144       assert(linked_xfb_info->Outputs[i].DstOffset == next_offset[buffer]);
 145
 146       next_offset[buffer] += linked_xfb_info->Outputs[i].NumComponents;
 147
 148       so_decl[i] = decl;
 149    }
 150
 151    BEGIN_BATCH(linked_xfb_info->NumOutputs * 2 + 3);
 152    OUT_BATCH(_3DSTATE_SO_DECL_LIST << 16 |
 153              (linked_xfb_info->NumOutputs * 2 + 1));
 154
 155    OUT_BATCH((buffer_mask << SO_STREAM_TO_BUFFER_SELECTS_0_SHIFT) |
 156              (0 << SO_STREAM_TO_BUFFER_SELECTS_1_SHIFT) |
 157              (0 << SO_STREAM_TO_BUFFER_SELECTS_2_SHIFT) |
 158              (0 << SO_STREAM_TO_BUFFER_SELECTS_3_SHIFT));
 159
 160    OUT_BATCH((linked_xfb_info->NumOutputs << SO_NUM_ENTRIES_0_SHIFT) |
 161              (0 << SO_NUM_ENTRIES_1_SHIFT) |
 162              (0 << SO_NUM_ENTRIES_2_SHIFT) |
 163              (0 << SO_NUM_ENTRIES_3_SHIFT));
 164
 165    for (i = 0; i < linked_xfb_info->NumOutputs; i++) {
 166       OUT_BATCH(so_decl[i]);
 167       OUT_BATCH(0);
 168    }
 169
 170    ADVANCE_BATCH();
 171 }
 172
 173 static void
 174 upload_3dstate_streamout(struct brw_context *brw, bool active,
 175                          struct brw_vue_map *vue_map)
 176 {
 177    struct intel_context *intel = &brw->intel;
 178    struct gl_context *ctx = &intel->ctx;
 179    /* _NEW_TRANSFORM_FEEDBACK */
 180    struct gl_transform_feedback_object *xfb_obj =
 181       ctx->TransformFeedback.CurrentObject;
 182    uint32_t dw1 = 0, dw2 = 0;
 183    int i;
 184
 185    /* _NEW_RASTERIZER_DISCARD */
 186    if (ctx->RasterDiscard)
 187       dw1 |= SO_RENDERING_DISABLE;
 188
 189    if (active) {
 190       int urb_entry_read_offset = 0;
 191       int urb_entry_read_length = (vue_map->num_slots + 1) / 2 -
 192          urb_entry_read_offset;
 193
 194       dw1 |= SO_FUNCTION_ENABLE;
 195       dw1 |= SO_STATISTICS_ENABLE;
 196
 197       /* _NEW_LIGHT */
 198       if (ctx->Light.ProvokingVertex != GL_FIRST_VERTEX_CONVENTION)
 199          dw1 |= SO_REORDER_TRAILING;
 200
 201       for (i = 0; i < 4; i++) {
 202          if (xfb_obj->Buffers[i]) {
 203             dw1 |= SO_BUFFER_ENABLE(i);
 204          }
 205       }
 206
 207       /* We always read the whole vertex.  This could be reduced at some
 208        * point by reading less and offsetting the register index in the
 209        * SO_DECLs.
 210        */
 211       dw2 |= urb_entry_read_offset << SO_STREAM_0_VERTEX_READ_OFFSET_SHIFT;
 212       dw2 |= (urb_entry_read_length - 1) <<
 213          SO_STREAM_0_VERTEX_READ_LENGTH_SHIFT;
 214    }
 215
 216    BEGIN_BATCH(3);
 217    OUT_BATCH(_3DSTATE_STREAMOUT << 16 | (3 - 2));
 218    OUT_BATCH(dw1);
 219    OUT_BATCH(dw2);
 220    ADVANCE_BATCH();
 221 }
 222
 223 static void
 224 upload_sol_state(struct brw_context *brw)
 225 {
 226    struct intel_context *intel = &brw->intel;
 227    struct gl_context *ctx = &intel->ctx;
 228    /* _NEW_TRANSFORM_FEEDBACK */
 229    struct gl_transform_feedback_object *xfb_obj =
 230       ctx->TransformFeedback.CurrentObject;
 231    bool active = xfb_obj->Active && !xfb_obj->Paused;
 232    struct brw_vue_map vue_map;
 233
 234    /* _NEW_TRANSFORM, CACHE_NEW_VS_PROG */
 235    brw_compute_vue_map(&vue_map, intel, ctx->Transform.ClipPlanesEnabled != 0,
 236                        brw->vs.prog_data->outputs_written);
 237
 238    if (active) {
 239       upload_3dstate_so_buffers(brw);
 240       upload_3dstate_so_decl_list(brw, &vue_map);
 241    }
 242
 243    /* Finally, set up the SOL stage.  This command must always follow updates to
 244     * the nonpipelined SOL state (3DSTATE_SO_BUFFER, 3DSTATE_SO_DECL_LIST) or
 245     * MMIO register updates (current performed by the kernel at each batch
 246     * emit).
 247     */
 248    upload_3dstate_streamout(brw, active, &vue_map);
 249 }
 250
 251 const struct brw_tracked_state gen7_sol_state = {
 252    .dirty = {
 253       .mesa  = (_NEW_RASTERIZER_DISCARD |
 254                 _NEW_LIGHT |
 255                 _NEW_TRANSFORM_FEEDBACK |
 256                 _NEW_TRANSFORM),
 257       .brw   = (BRW_NEW_BATCH |
 258                 BRW_NEW_VERTEX_PROGRAM),
 259       .cache = CACHE_NEW_VS_PROG,
 260    },
 261    .emit = upload_sol_state,
 262 };