src/mesa/drivers/dri/i965/gen7_sol_state.c

   1 /*
   2  * Copyright © 2011 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 /**
  25  * @file gen7_sol_state.c
  26  *
  27  * Controls the stream output logic (SOL) stage of the gen7 hardware, which is
  28  * used to implement GL_EXT_transform_feedback.
  29  */
  30
  31 #include "brw_context.h"
  32 #include "brw_state.h"
  33 #include "brw_defines.h"
  34 #include "intel_batchbuffer.h"
  35 #include "intel_buffer_objects.h"
  36 #include "main/transformfeedback.h"
  37
  38 static void
  39 upload_3dstate_so_buffers(struct brw_context *brw)
  40 {
  41    struct intel_context *intel = &brw->intel;
  42    struct gl_context *ctx = &intel->ctx;
  43    /* BRW_NEW_VERTEX_PROGRAM */
  44    const struct gl_shader_program *vs_prog =
  45       ctx->Shader.CurrentVertexProgram;
  46    const struct gl_transform_feedback_info *linked_xfb_info =
  47       &vs_prog->LinkedTransformFeedback;
  48    /* _NEW_TRANSFORM_FEEDBACK */
  49    struct gl_transform_feedback_object *xfb_obj =
  50       ctx->TransformFeedback.CurrentObject;
  51    int i;
  52
  53    /* Set up the up to 4 output buffers.  These are the ranges defined in the
  54     * gl_transform_feedback_object.
  55     */
  56    for (i = 0; i < 4; i++) {
  57       struct intel_buffer_object *bufferobj =
  58          intel_buffer_object(xfb_obj->Buffers[i]);
  59       drm_intel_bo *bo;
  60       uint32_t start, end;
  61       uint32_t stride;
  62
  63       if (!xfb_obj->Buffers[i]) {
  64          /* The pitch of 0 in this command indicates that the buffer is
  65           * unbound and won't be written to.
  66           */
  67          BEGIN_BATCH(4);
  68          OUT_BATCH(_3DSTATE_SO_BUFFER << 16 | (4 - 2));
  69          OUT_BATCH((i << SO_BUFFER_INDEX_SHIFT));
  70          OUT_BATCH(0);
  71          OUT_BATCH(0);
  72          ADVANCE_BATCH();
  73
  74          continue;
  75       }
  76
  77       bo = intel_bufferobj_buffer(intel, bufferobj, INTEL_WRITE_PART);
  78       stride = linked_xfb_info->BufferStride[i] * 4;
  79
  80       start = xfb_obj->Offset[i];
  81       assert(start % 4 == 0);
  82       end = ALIGN(start + xfb_obj->Size[i], 4);
  83       assert(end <= bo->size);
  84
  85       /* If we don't have hardware contexts, then we reset our offsets at the
  86        * start of every batch, so we track the number of vertices written in
  87        * software and increment our pointers by that many.
  88        */
  89       if (!intel->hw_ctx) {
  90          start += brw->sol.offset_0_batch_start * stride;
  91          assert(start <= end);
  92       }
  93
  94       BEGIN_BATCH(4);
  95       OUT_BATCH(_3DSTATE_SO_BUFFER << 16 | (4 - 2));
  96       OUT_BATCH((i << SO_BUFFER_INDEX_SHIFT) | stride);
  97       OUT_RELOC(bo, I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, start);
  98       OUT_RELOC(bo, I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, end);
  99       ADVANCE_BATCH();
 100    }
 101 }
 102
 103 /**
 104  * Outputs the 3DSTATE_SO_DECL_LIST command.
 105  *
 106  * The data output is a series of 64-bit entries containing a SO_DECL per
 107  * stream.  We only have one stream of rendering coming out of the GS unit, so
 108  * we only emit stream 0 (low 16 bits) SO_DECLs.
 109  */
 110 static void
 111 upload_3dstate_so_decl_list(struct brw_context *brw,
 112                             const struct brw_vue_map *vue_map)
 113 {
 114    struct intel_context *intel = &brw->intel;
 115    struct gl_context *ctx = &intel->ctx;
 116    /* BRW_NEW_VERTEX_PROGRAM */
 117    const struct gl_shader_program *vs_prog =
 118       ctx->Shader.CurrentVertexProgram;
 119    /* _NEW_TRANSFORM_FEEDBACK */
 120    const struct gl_transform_feedback_info *linked_xfb_info =
 121       &vs_prog->LinkedTransformFeedback;
 122    int i;
 123    uint16_t so_decl[128];
 124    int buffer_mask = 0;
 125    int next_offset[4] = {0, 0, 0, 0};
 126
 127    STATIC_ASSERT(ARRAY_SIZE(so_decl) >= MAX_PROGRAM_OUTPUTS);
 128
 129    /* Construct the list of SO_DECLs to be emitted.  The formatting of the
 130     * command is feels strange -- each dword pair contains a SO_DECL per stream.
 131     */
 132    for (i = 0; i < linked_xfb_info->NumOutputs; i++) {
 133       int buffer = linked_xfb_info->Outputs[i].OutputBuffer;
 134       uint16_t decl = 0;
 135       int varying = linked_xfb_info->Outputs[i].OutputRegister;
 136       unsigned component_mask =
 137          (1 << linked_xfb_info->Outputs[i].NumComponents) - 1;
 138
 139       /* gl_PointSize is stored in VARYING_SLOT_PSIZ.w. */
 140       if (varying == VARYING_SLOT_PSIZ) {
 141          assert(linked_xfb_info->Outputs[i].NumComponents == 1);
 142          component_mask <<= 3;
 143       } else {
 144          component_mask <<= linked_xfb_info->Outputs[i].ComponentOffset;
 145       }
 146
 147       buffer_mask |= 1 << buffer;
 148
 149       decl |= buffer << SO_DECL_OUTPUT_BUFFER_SLOT_SHIFT;
 150       decl |= vue_map->varying_to_slot[varying] <<
 151          SO_DECL_REGISTER_INDEX_SHIFT;
 152       decl |= component_mask << SO_DECL_COMPONENT_MASK_SHIFT;
 153
 154       /* This assert should be true until GL_ARB_transform_feedback_instanced
 155        * is added and we start using the hole flag.
 156        */
 157       assert(linked_xfb_info->Outputs[i].DstOffset == next_offset[buffer]);
 158
 159       next_offset[buffer] += linked_xfb_info->Outputs[i].NumComponents;
 160
 161       so_decl[i] = decl;
 162    }
 163
 164    BEGIN_BATCH(linked_xfb_info->NumOutputs * 2 + 3);
 165    OUT_BATCH(_3DSTATE_SO_DECL_LIST << 16 |
 166              (linked_xfb_info->NumOutputs * 2 + 1));
 167
 168    OUT_BATCH((buffer_mask << SO_STREAM_TO_BUFFER_SELECTS_0_SHIFT) |
 169              (0 << SO_STREAM_TO_BUFFER_SELECTS_1_SHIFT) |
 170              (0 << SO_STREAM_TO_BUFFER_SELECTS_2_SHIFT) |
 171              (0 << SO_STREAM_TO_BUFFER_SELECTS_3_SHIFT));
 172
 173    OUT_BATCH((linked_xfb_info->NumOutputs << SO_NUM_ENTRIES_0_SHIFT) |
 174              (0 << SO_NUM_ENTRIES_1_SHIFT) |
 175              (0 << SO_NUM_ENTRIES_2_SHIFT) |
 176              (0 << SO_NUM_ENTRIES_3_SHIFT));
 177
 178    for (i = 0; i < linked_xfb_info->NumOutputs; i++) {
 179       OUT_BATCH(so_decl[i]);
 180       OUT_BATCH(0);
 181    }
 182
 183    ADVANCE_BATCH();
 184 }
 185
 186 static void
 187 upload_3dstate_streamout(struct brw_context *brw, bool active,
 188                          const struct brw_vue_map *vue_map)
 189 {
 190    struct intel_context *intel = &brw->intel;
 191    struct gl_context *ctx = &intel->ctx;
 192    /* _NEW_TRANSFORM_FEEDBACK */
 193    struct gl_transform_feedback_object *xfb_obj =
 194       ctx->TransformFeedback.CurrentObject;
 195    uint32_t dw1 = 0, dw2 = 0;
 196    int i;
 197
 198    /* _NEW_RASTERIZER_DISCARD */
 199    if (ctx->RasterDiscard)
 200       dw1 |= SO_RENDERING_DISABLE;
 201
 202    if (active) {
 203       int urb_entry_read_offset = 0;
 204       int urb_entry_read_length = (vue_map->num_slots + 1) / 2 -
 205          urb_entry_read_offset;
 206
 207       dw1 |= SO_FUNCTION_ENABLE;
 208       dw1 |= SO_STATISTICS_ENABLE;
 209
 210       /* _NEW_LIGHT */
 211       if (ctx->Light.ProvokingVertex != GL_FIRST_VERTEX_CONVENTION)
 212          dw1 |= SO_REORDER_TRAILING;
 213
 214       for (i = 0; i < 4; i++) {
 215          if (xfb_obj->Buffers[i]) {
 216             dw1 |= SO_BUFFER_ENABLE(i);
 217          }
 218       }
 219
 220       /* We always read the whole vertex.  This could be reduced at some
 221        * point by reading less and offsetting the register index in the
 222        * SO_DECLs.
 223        */
 224       dw2 |= urb_entry_read_offset << SO_STREAM_0_VERTEX_READ_OFFSET_SHIFT;
 225       dw2 |= (urb_entry_read_length - 1) <<
 226          SO_STREAM_0_VERTEX_READ_LENGTH_SHIFT;
 227    }
 228
 229    BEGIN_BATCH(3);
 230    OUT_BATCH(_3DSTATE_STREAMOUT << 16 | (3 - 2));
 231    OUT_BATCH(dw1);
 232    OUT_BATCH(dw2);
 233    ADVANCE_BATCH();
 234 }
 235
 236 static void
 237 upload_sol_state(struct brw_context *brw)
 238 {
 239    struct intel_context *intel = &brw->intel;
 240    struct gl_context *ctx = &intel->ctx;
 241    /* _NEW_TRANSFORM_FEEDBACK */
 242    bool active = _mesa_is_xfb_active_and_unpaused(ctx);
 243
 244    if (active) {
 245       upload_3dstate_so_buffers(brw);
 246       /* BRW_NEW_VUE_MAP_GEOM_OUT */
 247       upload_3dstate_so_decl_list(brw, &brw->vue_map_geom_out);
 248
 249       /* If we don't have hardware contexts, then some other client may have
 250        * changed the SO write offsets, and we need to rewrite them.
 251        */
 252       if (!intel->hw_ctx)
 253          intel->batch.needs_sol_reset = true;
 254    }
 255
 256    /* Finally, set up the SOL stage.  This command must always follow updates to
 257     * the nonpipelined SOL state (3DSTATE_SO_BUFFER, 3DSTATE_SO_DECL_LIST) or
 258     * MMIO register updates (current performed by the kernel at each batch
 259     * emit).
 260     */
 261    upload_3dstate_streamout(brw, active, &brw->vue_map_geom_out);
 262 }
 263
 264 const struct brw_tracked_state gen7_sol_state = {
 265    .dirty = {
 266       .mesa  = (_NEW_RASTERIZER_DISCARD |
 267                 _NEW_LIGHT |
 268                 _NEW_TRANSFORM_FEEDBACK),
 269       .brw   = (BRW_NEW_BATCH |
 270                 BRW_NEW_VERTEX_PROGRAM |
 271                 BRW_NEW_VUE_MAP_GEOM_OUT)
 272    },
 273    .emit = upload_sol_state,
 274 };
 275
 276 void
 277 gen7_end_transform_feedback(struct gl_context *ctx,
 278                             struct gl_transform_feedback_object *obj)
 279 {
 280    /* Because we have to rely on the kernel to reset our SO write offsets, and
 281     * we only get to do it once per batchbuffer, flush the batch after feedback
 282     * so another transform feedback can get the write offset reset it needs.
 283     *
 284     * This also covers any cache flushing required.
 285     */
 286    struct brw_context *brw = brw_context(ctx);
 287    struct intel_context *intel = &brw->intel;
 288
 289    intel_batchbuffer_flush(intel);
 290 }