2 * Copyright © 2011 Intel Corporation
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9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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24 #include "main/macros.h"
25 #include "intel_batchbuffer.h"
26 #include "brw_context.h"
27 #include "brw_state.h"
28 #include "brw_defines.h"
31 * The following diagram shows how we partition the URB:
33 * 8kB 8kB Rest of the URB space
34 * ____-____ ____-____ _________________-_________________
36 * +-------------------------------------------------------------+
37 * | VS Push | FS Push | VS |
38 * | Constants | Constants | Handles |
39 * +-------------------------------------------------------------+
41 * Notably, push constants must be stored at the beginning of the URB
42 * space, while entries can be stored anywhere. Ivybridge and Haswell
43 * GT1/GT2 have a maximum constant buffer size of 16kB, while Haswell GT3
44 * doubles this (32kB).
46 * Currently we split the constant buffer space evenly between VS and FS.
47 * This is probably not ideal, but simple.
49 * Ivybridge GT1 and Haswell GT1 have 128kB of URB space.
50 * Ivybridge GT2 and Haswell GT2 have 256kB of URB space.
51 * Haswell GT3 has 512kB of URB space.
53 * See "Volume 2a: 3D Pipeline," section 1.8, "Volume 1b: Configurations",
54 * and the documentation for 3DSTATE_PUSH_CONSTANT_ALLOC_xS.
57 gen7_allocate_push_constants(struct brw_context
*brw
)
59 struct intel_context
*intel
= &brw
->intel
;
62 if (intel
->is_haswell
&& intel
->gt
== 3)
66 OUT_BATCH(_3DSTATE_PUSH_CONSTANT_ALLOC_VS
<< 16 | (2 - 2));
71 OUT_BATCH(_3DSTATE_PUSH_CONSTANT_ALLOC_PS
<< 16 | (2 - 2));
72 OUT_BATCH(size
| size
<< GEN7_PUSH_CONSTANT_BUFFER_OFFSET_SHIFT
);
77 gen7_upload_urb(struct brw_context
*brw
)
79 struct intel_context
*intel
= &brw
->intel
;
80 const int push_size_kB
= intel
->is_haswell
&& intel
->gt
== 3 ? 32 : 16;
82 /* Total space for entries is URB size - 16kB for push constants */
83 int handle_region_size
= (brw
->urb
.size
- push_size_kB
) * 1024; /* bytes */
85 /* CACHE_NEW_VS_PROG */
86 unsigned vs_size
= MAX2(brw
->vs
.prog_data
->base
.urb_entry_size
, 1);
88 int nr_vs_entries
= handle_region_size
/ (vs_size
* 64);
89 if (nr_vs_entries
> brw
->urb
.max_vs_entries
)
90 nr_vs_entries
= brw
->urb
.max_vs_entries
;
92 /* According to volume 2a, nr_vs_entries must be a multiple of 8. */
93 brw
->urb
.nr_vs_entries
= ROUND_DOWN_TO(nr_vs_entries
, 8);
95 /* URB Starting Addresses are specified in multiples of 8kB. */
96 brw
->urb
.vs_start
= push_size_kB
/ 8; /* skip over push constants */
98 assert(brw
->urb
.nr_vs_entries
% 8 == 0);
99 assert(brw
->urb
.nr_gs_entries
% 8 == 0);
101 assert(!brw
->gs
.prog_active
);
103 gen7_emit_vs_workaround_flush(intel
);
104 gen7_emit_urb_state(brw
, brw
->urb
.nr_vs_entries
, vs_size
, brw
->urb
.vs_start
);
108 gen7_emit_urb_state(struct brw_context
*brw
, GLuint nr_vs_entries
,
109 GLuint vs_size
, GLuint vs_start
)
111 struct intel_context
*intel
= &brw
->intel
;
114 OUT_BATCH(_3DSTATE_URB_VS
<< 16 | (2 - 2));
115 OUT_BATCH(nr_vs_entries
|
116 ((vs_size
- 1) << GEN7_URB_ENTRY_SIZE_SHIFT
) |
117 (vs_start
<< GEN7_URB_STARTING_ADDRESS_SHIFT
));
120 /* Allocate the GS, HS, and DS zero space - we don't use them. */
122 OUT_BATCH(_3DSTATE_URB_GS
<< 16 | (2 - 2));
123 OUT_BATCH((0 << GEN7_URB_ENTRY_SIZE_SHIFT
) |
124 (vs_start
<< GEN7_URB_STARTING_ADDRESS_SHIFT
));
128 OUT_BATCH(_3DSTATE_URB_HS
<< 16 | (2 - 2));
129 OUT_BATCH((0 << GEN7_URB_ENTRY_SIZE_SHIFT
) |
130 (vs_start
<< GEN7_URB_STARTING_ADDRESS_SHIFT
));
134 OUT_BATCH(_3DSTATE_URB_DS
<< 16 | (2 - 2));
135 OUT_BATCH((0 << GEN7_URB_ENTRY_SIZE_SHIFT
) |
136 (vs_start
<< GEN7_URB_STARTING_ADDRESS_SHIFT
));
140 const struct brw_tracked_state gen7_urb
= {
143 .brw
= BRW_NEW_CONTEXT
,
144 .cache
= (CACHE_NEW_VS_PROG
| CACHE_NEW_GS_PROG
),
146 .emit
= gen7_upload_urb
,