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11 * The above copyright notice and this permission notice (including the next
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16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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24 #include "main/macros.h"
25 #include "intel_batchbuffer.h"
26 #include "brw_context.h"
27 #include "brw_state.h"
28 #include "brw_defines.h"
31 * The following diagram shows how we partition the URB:
33 * 8kB 8kB Rest of the URB space
34 * ____-____ ____-____ _________________-_________________
36 * +-------------------------------------------------------------+
37 * | VS Push | FS Push | VS |
38 * | Constants | Constants | Handles |
39 * +-------------------------------------------------------------+
41 * Notably, push constants must be stored at the beginning of the URB
42 * space, while entries can be stored anywhere. Ivybridge has a maximum
43 * constant buffer size of 16kB.
45 * Currently we split the constant buffer space evenly between VS and FS.
46 * This is probably not ideal, but simple.
48 * Ivybridge GT1 has 128kB of URB space.
49 * Ivybridge GT2 has 256kB of URB space.
51 * See "Volume 2a: 3D Pipeline," section 1.8.
54 gen7_upload_urb(struct brw_context
*brw
)
56 struct intel_context
*intel
= &brw
->intel
;
57 /* Total space for entries is URB size - 16kB for push constants */
58 int handle_region_size
= (brw
->urb
.size
- 16) * 1024; /* bytes */
60 /* CACHE_NEW_VS_PROG */
61 brw
->urb
.vs_size
= MAX2(brw
->vs
.prog_data
->urb_entry_size
, 1);
63 int nr_vs_entries
= handle_region_size
/ (brw
->urb
.vs_size
* 64);
64 if (nr_vs_entries
> brw
->urb
.max_vs_entries
)
65 nr_vs_entries
= brw
->urb
.max_vs_entries
;
67 /* According to volume 2a, nr_vs_entries must be a multiple of 8. */
68 brw
->urb
.nr_vs_entries
= ROUND_DOWN_TO(nr_vs_entries
, 8);
70 /* URB Starting Addresses are specified in multiples of 8kB. */
71 brw
->urb
.vs_start
= 2; /* skip over push constants */
73 assert(brw
->urb
.nr_vs_entries
% 8 == 0);
74 assert(brw
->urb
.nr_gs_entries
% 8 == 0);
76 assert(!brw
->gs
.prog_active
);
79 OUT_BATCH(_3DSTATE_PUSH_CONSTANT_ALLOC_VS
<< 16 | (2 - 2));
84 OUT_BATCH(_3DSTATE_PUSH_CONSTANT_ALLOC_PS
<< 16 | (2 - 2));
85 OUT_BATCH(8 | 8 << GEN7_PUSH_CONSTANT_BUFFER_OFFSET_SHIFT
);
89 OUT_BATCH(_3DSTATE_URB_VS
<< 16 | (2 - 2));
90 OUT_BATCH(brw
->urb
.nr_vs_entries
|
91 ((brw
->urb
.vs_size
- 1) << GEN7_URB_ENTRY_SIZE_SHIFT
) |
92 (brw
->urb
.vs_start
<< GEN7_URB_STARTING_ADDRESS_SHIFT
));
95 /* Allocate the GS, HS, and DS zero space - we don't use them. */
97 OUT_BATCH(_3DSTATE_URB_GS
<< 16 | (2 - 2));
98 OUT_BATCH((0 << GEN7_URB_ENTRY_SIZE_SHIFT
) |
99 (2 << GEN7_URB_STARTING_ADDRESS_SHIFT
));
103 OUT_BATCH(_3DSTATE_URB_HS
<< 16 | (2 - 2));
104 OUT_BATCH((0 << GEN7_URB_ENTRY_SIZE_SHIFT
) |
105 (2 << GEN7_URB_STARTING_ADDRESS_SHIFT
));
109 OUT_BATCH(_3DSTATE_URB_DS
<< 16 | (2 - 2));
110 OUT_BATCH((0 << GEN7_URB_ENTRY_SIZE_SHIFT
) |
111 (2 << GEN7_URB_STARTING_ADDRESS_SHIFT
));
115 const struct brw_tracked_state gen7_urb
= {
118 .brw
= BRW_NEW_CONTEXT
,
119 .cache
= (CACHE_NEW_VS_PROG
| CACHE_NEW_GS_PROG
),
121 .emit
= gen7_upload_urb
,