src/mesa/drivers/dri/i965/gen7_urb.c

   1 /*
   2  * Copyright © 2011 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include "main/macros.h"
  25 #include "intel_batchbuffer.h"
  26 #include "brw_context.h"
  27 #include "brw_state.h"
  28 #include "brw_defines.h"
  29
  30 /**
  31  * The following diagram shows how we partition the URB:
  32  *
  33  *      8kB         8kB              Rest of the URB space
  34  *   ____-____   ____-____   _________________-_________________
  35  *  /         \ /         \ /                                   \
  36  * +-------------------------------------------------------------+
  37  * | VS Push   | FS Push   | VS                                  |
  38  * | Constants | Constants | Handles                             |
  39  * +-------------------------------------------------------------+
  40  *
  41  * Notably, push constants must be stored at the beginning of the URB
  42  * space, while entries can be stored anywhere.  Ivybridge has a maximum
  43  * constant buffer size of 16kB.
  44  *
  45  * Currently we split the constant buffer space evenly between VS and FS.
  46  * This is probably not ideal, but simple.
  47  *
  48  * Ivybridge GT1 has 128kB of URB space.
  49  * Ivybridge GT2 has 256kB of URB space.
  50  *
  51  * See "Volume 2a: 3D Pipeline," section 1.8.
  52  */
  53 static void
  54 gen7_upload_urb(struct brw_context *brw)
  55 {
  56    struct intel_context *intel = &brw->intel;
  57    /* Total space for entries is URB size - 16kB for push constants */
  58    int handle_region_size = (brw->urb.size - 16) * 1024; /* bytes */
  59
  60    /* CACHE_NEW_VS_PROG */
  61    brw->urb.vs_size = MAX2(brw->vs.prog_data->urb_entry_size, 1);
  62
  63    int nr_vs_entries = handle_region_size / (brw->urb.vs_size * 64);
  64    if (nr_vs_entries > brw->urb.max_vs_entries)
  65       nr_vs_entries = brw->urb.max_vs_entries;
  66
  67    /* According to volume 2a, nr_vs_entries must be a multiple of 8. */
  68    brw->urb.nr_vs_entries = ROUND_DOWN_TO(nr_vs_entries, 8);
  69
  70    /* URB Starting Addresses are specified in multiples of 8kB. */
  71    brw->urb.vs_start = 2; /* skip over push constants */
  72
  73    assert(brw->urb.nr_vs_entries % 8 == 0);
  74    assert(brw->urb.nr_gs_entries % 8 == 0);
  75    /* GS requirement */
  76    assert(!brw->gs.prog_active);
  77
  78    BEGIN_BATCH(2);
  79    OUT_BATCH(_3DSTATE_PUSH_CONSTANT_ALLOC_VS << 16 | (2 - 2));
  80    OUT_BATCH(8);
  81    ADVANCE_BATCH();
  82
  83    BEGIN_BATCH(2);
  84    OUT_BATCH(_3DSTATE_PUSH_CONSTANT_ALLOC_PS << 16 | (2 - 2));
  85    OUT_BATCH(8 | 8 << GEN7_PUSH_CONSTANT_BUFFER_OFFSET_SHIFT);
  86    ADVANCE_BATCH();
  87
  88    BEGIN_BATCH(2);
  89    OUT_BATCH(_3DSTATE_URB_VS << 16 | (2 - 2));
  90    OUT_BATCH(brw->urb.nr_vs_entries |
  91              ((brw->urb.vs_size - 1) << GEN7_URB_ENTRY_SIZE_SHIFT) |
  92              (brw->urb.vs_start << GEN7_URB_STARTING_ADDRESS_SHIFT));
  93    ADVANCE_BATCH();
  94
  95    /* Allocate the GS, HS, and DS zero space - we don't use them. */
  96    BEGIN_BATCH(2);
  97    OUT_BATCH(_3DSTATE_URB_GS << 16 | (2 - 2));
  98    OUT_BATCH((0 << GEN7_URB_ENTRY_SIZE_SHIFT) |
  99              (2 << GEN7_URB_STARTING_ADDRESS_SHIFT));
 100    ADVANCE_BATCH();
 101
 102    BEGIN_BATCH(2);
 103    OUT_BATCH(_3DSTATE_URB_HS << 16 | (2 - 2));
 104    OUT_BATCH((0 << GEN7_URB_ENTRY_SIZE_SHIFT) |
 105              (2 << GEN7_URB_STARTING_ADDRESS_SHIFT));
 106    ADVANCE_BATCH();
 107
 108    BEGIN_BATCH(2);
 109    OUT_BATCH(_3DSTATE_URB_DS << 16 | (2 - 2));
 110    OUT_BATCH((0 << GEN7_URB_ENTRY_SIZE_SHIFT) |
 111              (2 << GEN7_URB_STARTING_ADDRESS_SHIFT));
 112    ADVANCE_BATCH();
 113 }
 114
 115 const struct brw_tracked_state gen7_urb = {
 116    .dirty = {
 117       .mesa = 0,
 118       .brw = BRW_NEW_CONTEXT,
 119       .cache = (CACHE_NEW_VS_PROG | CACHE_NEW_GS_PROG),
 120    },
 121    .emit = gen7_upload_urb,
 122 };