src/mesa/drivers/dri/i965/gen7_urb.c

   1 /*
   2  * Copyright © 2011 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include "main/macros.h"
  25 #include "intel_batchbuffer.h"
  26 #include "brw_context.h"
  27 #include "brw_state.h"
  28 #include "brw_defines.h"
  29
  30 #include "common/gen_l3_config.h"
  31
  32 /**
  33  * The following diagram shows how we partition the URB:
  34  *
  35  *        16kB or 32kB               Rest of the URB space
  36  *   __________-__________   _________________-_________________
  37  *  /                     \ /                                   \
  38  * +-------------------------------------------------------------+
  39  * |  VS/HS/DS/GS/FS Push  |           VS/HS/DS/GS URB           |
  40  * |       Constants       |               Entries               |
  41  * +-------------------------------------------------------------+
  42  *
  43  * Notably, push constants must be stored at the beginning of the URB
  44  * space, while entries can be stored anywhere.  Ivybridge and Haswell
  45  * GT1/GT2 have a maximum constant buffer size of 16kB, while Haswell GT3
  46  * doubles this (32kB).
  47  *
  48  * Ivybridge and Haswell GT1/GT2 allow push constants to be located (and
  49  * sized) in increments of 1kB.  Haswell GT3 requires them to be located and
  50  * sized in increments of 2kB.
  51  *
  52  * Currently we split the constant buffer space evenly among whatever stages
  53  * are active.  This is probably not ideal, but simple.
  54  *
  55  * Ivybridge GT1 and Haswell GT1 have 128kB of URB space.
  56  * Ivybridge GT2 and Haswell GT2 have 256kB of URB space.
  57  * Haswell GT3 has 512kB of URB space.
  58  *
  59  * See "Volume 2a: 3D Pipeline," section 1.8, "Volume 1b: Configurations",
  60  * and the documentation for 3DSTATE_PUSH_CONSTANT_ALLOC_xS.
  61  */
  62 static void
  63 gen7_allocate_push_constants(struct brw_context *brw)
  64 {
  65    const struct gen_device_info *devinfo = &brw->screen->devinfo;
  66
  67    /* BRW_NEW_GEOMETRY_PROGRAM */
  68    bool gs_present = brw->programs[MESA_SHADER_GEOMETRY];
  69
  70    /* BRW_NEW_TESS_PROGRAMS */
  71    bool tess_present = brw->programs[MESA_SHADER_TESS_EVAL];
  72
  73    unsigned avail_size = 16;
  74    unsigned multiplier =
  75       (devinfo->gen >= 8 || (devinfo->is_haswell && devinfo->gt == 3)) ? 2 : 1;
  76
  77    int stages = 2 + gs_present + 2 * tess_present;
  78
  79    /* Divide up the available space equally between stages.  Because we
  80     * round down (using floor division), there may be some left over
  81     * space.  We allocate that to the pixel shader stage.
  82     */
  83    unsigned size_per_stage = avail_size / stages;
  84
  85    unsigned vs_size = size_per_stage;
  86    unsigned hs_size = tess_present ? size_per_stage : 0;
  87    unsigned ds_size = tess_present ? size_per_stage : 0;
  88    unsigned gs_size = gs_present ? size_per_stage : 0;
  89    unsigned fs_size = avail_size - size_per_stage * (stages - 1);
  90
  91    gen7_emit_push_constant_state(brw, multiplier * vs_size,
  92                                  multiplier * hs_size, multiplier * ds_size,
  93                                  multiplier * gs_size, multiplier * fs_size);
  94
  95    /* From p115 of the Ivy Bridge PRM (3.2.1.4 3DSTATE_PUSH_CONSTANT_ALLOC_VS):
  96     *
  97     *     Programming Restriction:
  98     *
  99     *     The 3DSTATE_CONSTANT_VS must be reprogrammed prior to the next
 100     *     3DPRIMITIVE command after programming the
 101     *     3DSTATE_PUSH_CONSTANT_ALLOC_VS.
 102     *
 103     * Similar text exists for the other 3DSTATE_PUSH_CONSTANT_ALLOC_*
 104     * commands.
 105     */
 106    brw->vs.base.push_constants_dirty = true;
 107    brw->tcs.base.push_constants_dirty = true;
 108    brw->tes.base.push_constants_dirty = true;
 109    brw->gs.base.push_constants_dirty = true;
 110    brw->wm.base.push_constants_dirty = true;
 111 }
 112
 113 void
 114 gen7_emit_push_constant_state(struct brw_context *brw, unsigned vs_size,
 115                               unsigned hs_size, unsigned ds_size,
 116                               unsigned gs_size, unsigned fs_size)
 117 {
 118    const struct gen_device_info *devinfo = &brw->screen->devinfo;
 119    unsigned offset = 0;
 120
 121    /* From the SKL PRM, Workarounds section (#878):
 122     *
 123     *    Push constant buffer corruption possible. WA: Insert 2 zero-length
 124     *    PushConst_PS before every intended PushConst_PS update, issue a
 125     *    NULLPRIM after each of the zero len PC update to make sure CS commits
 126     *    them.
 127     *
 128     * This workaround is attempting to solve a pixel shader push constant
 129     * synchronization issue.
 130     *
 131     * There's an unpublished WA that involves re-emitting
 132     * 3DSTATE_PUSH_CONSTANT_ALLOC_PS for every 500-ish 3DSTATE_CONSTANT_PS
 133     * packets. Since our counting methods may not be reliable due to
 134     * context-switching and pre-emption, we instead choose to approximate this
 135     * behavior by re-emitting the packet at the top of the batch.
 136     */
 137    if (brw->ctx.NewDriverState == BRW_NEW_BATCH) {
 138        /* SKL GT2 and GLK 2x6 have reliably demonstrated this issue thus far.
 139         * We've also seen some intermittent failures from SKL GT4 and BXT in
 140         * the past.
 141         */
 142       if (!devinfo->is_skylake &&
 143           !devinfo->is_broxton &&
 144           !devinfo->is_geminilake)
 145          return;
 146    }
 147
 148    BEGIN_BATCH(10);
 149    OUT_BATCH(_3DSTATE_PUSH_CONSTANT_ALLOC_VS << 16 | (2 - 2));
 150    OUT_BATCH(vs_size | offset << GEN7_PUSH_CONSTANT_BUFFER_OFFSET_SHIFT);
 151    offset += vs_size;
 152
 153    OUT_BATCH(_3DSTATE_PUSH_CONSTANT_ALLOC_HS << 16 | (2 - 2));
 154    OUT_BATCH(hs_size | offset << GEN7_PUSH_CONSTANT_BUFFER_OFFSET_SHIFT);
 155    offset += hs_size;
 156
 157    OUT_BATCH(_3DSTATE_PUSH_CONSTANT_ALLOC_DS << 16 | (2 - 2));
 158    OUT_BATCH(ds_size | offset << GEN7_PUSH_CONSTANT_BUFFER_OFFSET_SHIFT);
 159    offset += ds_size;
 160
 161    OUT_BATCH(_3DSTATE_PUSH_CONSTANT_ALLOC_GS << 16 | (2 - 2));
 162    OUT_BATCH(gs_size | offset << GEN7_PUSH_CONSTANT_BUFFER_OFFSET_SHIFT);
 163    offset += gs_size;
 164
 165    OUT_BATCH(_3DSTATE_PUSH_CONSTANT_ALLOC_PS << 16 | (2 - 2));
 166    OUT_BATCH(fs_size | offset << GEN7_PUSH_CONSTANT_BUFFER_OFFSET_SHIFT);
 167    ADVANCE_BATCH();
 168
 169    /* From p292 of the Ivy Bridge PRM (11.2.4 3DSTATE_PUSH_CONSTANT_ALLOC_PS):
 170     *
 171     *     A PIPE_CONTROL command with the CS Stall bit set must be programmed
 172     *     in the ring after this instruction.
 173     *
 174     * No such restriction exists for Haswell or Baytrail.
 175     */
 176    if (devinfo->gen < 8 && !devinfo->is_haswell && !devinfo->is_baytrail)
 177       gen7_emit_cs_stall_flush(brw);
 178 }
 179
 180 const struct brw_tracked_state gen7_push_constant_space = {
 181    .dirty = {
 182       .mesa = 0,
 183       .brw = BRW_NEW_CONTEXT |
 184              BRW_NEW_BATCH | /* Push constant workaround */
 185              BRW_NEW_GEOMETRY_PROGRAM |
 186              BRW_NEW_TESS_PROGRAMS,
 187    },
 188    .emit = gen7_allocate_push_constants,
 189 };
 190
 191 static void
 192 upload_urb(struct brw_context *brw)
 193 {
 194    /* BRW_NEW_VS_PROG_DATA */
 195    const struct brw_vue_prog_data *vs_vue_prog_data =
 196       brw_vue_prog_data(brw->vs.base.prog_data);
 197    const unsigned vs_size = MAX2(vs_vue_prog_data->urb_entry_size, 1);
 198    /* BRW_NEW_GS_PROG_DATA */
 199    const bool gs_present = brw->gs.base.prog_data;
 200    /* BRW_NEW_TES_PROG_DATA */
 201    const bool tess_present = brw->tes.base.prog_data;
 202
 203    gen7_upload_urb(brw, vs_size, gs_present, tess_present);
 204 }
 205
 206 void
 207 gen7_upload_urb(struct brw_context *brw, unsigned vs_size,
 208                 bool gs_present, bool tess_present)
 209 {
 210    const struct gen_device_info *devinfo = &brw->screen->devinfo;
 211    const int push_size_kB =
 212       (devinfo->gen >= 8 || (devinfo->is_haswell && devinfo->gt == 3)) ? 32 : 16;
 213
 214    /* BRW_NEW_{VS,TCS,TES,GS}_PROG_DATA */
 215    struct brw_vue_prog_data *prog_data[4] = {
 216       [MESA_SHADER_VERTEX] =
 217          brw_vue_prog_data(brw->vs.base.prog_data),
 218       [MESA_SHADER_TESS_CTRL] =
 219          tess_present ? brw_vue_prog_data(brw->tcs.base.prog_data) : NULL,
 220       [MESA_SHADER_TESS_EVAL] =
 221          tess_present ? brw_vue_prog_data(brw->tes.base.prog_data) : NULL,
 222       [MESA_SHADER_GEOMETRY] =
 223          gs_present ? brw_vue_prog_data(brw->gs.base.prog_data) : NULL,
 224    };
 225
 226    unsigned entry_size[4];
 227    entry_size[MESA_SHADER_VERTEX] = vs_size;
 228    for (int i = MESA_SHADER_TESS_CTRL; i <= MESA_SHADER_GEOMETRY; i++) {
 229       entry_size[i] = prog_data[i] ? prog_data[i]->urb_entry_size : 1;
 230    }
 231
 232    /* If we're just switching between programs with the same URB requirements,
 233     * skip the rest of the logic.
 234     */
 235    if (brw->urb.vsize == entry_size[MESA_SHADER_VERTEX] &&
 236        brw->urb.gs_present == gs_present &&
 237        brw->urb.gsize == entry_size[MESA_SHADER_GEOMETRY] &&
 238        brw->urb.tess_present == tess_present &&
 239        brw->urb.hsize == entry_size[MESA_SHADER_TESS_CTRL] &&
 240        brw->urb.dsize == entry_size[MESA_SHADER_TESS_EVAL]) {
 241       return;
 242    }
 243    brw->urb.vsize = entry_size[MESA_SHADER_VERTEX];
 244    brw->urb.gs_present = gs_present;
 245    brw->urb.gsize = entry_size[MESA_SHADER_GEOMETRY];
 246    brw->urb.tess_present = tess_present;
 247    brw->urb.hsize = entry_size[MESA_SHADER_TESS_CTRL];
 248    brw->urb.dsize = entry_size[MESA_SHADER_TESS_EVAL];
 249
 250    unsigned entries[4];
 251    unsigned start[4];
 252    gen_get_urb_config(devinfo, 1024 * push_size_kB, 1024 * brw->urb.size,
 253                       tess_present, gs_present, entry_size, entries, start);
 254
 255    if (devinfo->gen == 7 && !devinfo->is_haswell && !devinfo->is_baytrail)
 256       gen7_emit_vs_workaround_flush(brw);
 257
 258    BEGIN_BATCH(8);
 259    for (int i = MESA_SHADER_VERTEX; i <= MESA_SHADER_GEOMETRY; i++) {
 260       assert(devinfo->gen != 10 || entry_size[i] % 3);
 261       OUT_BATCH((_3DSTATE_URB_VS + i) << 16 | (2 - 2));
 262       OUT_BATCH(entries[i] |
 263                 ((entry_size[i] - 1) << GEN7_URB_ENTRY_SIZE_SHIFT) |
 264                 (start[i] << GEN7_URB_STARTING_ADDRESS_SHIFT));
 265    }
 266    ADVANCE_BATCH();
 267 }
 268
 269 const struct brw_tracked_state gen7_urb = {
 270    .dirty = {
 271       .mesa = 0,
 272       .brw = BRW_NEW_BLORP |
 273              BRW_NEW_CONTEXT |
 274              BRW_NEW_URB_SIZE |
 275              BRW_NEW_GS_PROG_DATA |
 276              BRW_NEW_TCS_PROG_DATA |
 277              BRW_NEW_TES_PROG_DATA |
 278              BRW_NEW_VS_PROG_DATA,
 279    },
 280    .emit = upload_urb,
 281 };