src/mesa/drivers/dri/i965/gen7_urb.c

   1 /*
   2  * Copyright © 2011 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include "main/macros.h"
  25 #include "intel_batchbuffer.h"
  26 #include "brw_context.h"
  27 #include "brw_state.h"
  28 #include "brw_defines.h"
  29
  30 /**
  31  * The following diagram shows how we partition the URB:
  32  *
  33  *        16kB or 32kB               Rest of the URB space
  34  *   __________-__________   _________________-_________________
  35  *  /                     \ /                                   \
  36  * +-------------------------------------------------------------+
  37  * |  VS/HS/DS/GS/FS Push  |           VS/HS/DS/GS URB           |
  38  * |       Constants       |               Entries               |
  39  * +-------------------------------------------------------------+
  40  *
  41  * Notably, push constants must be stored at the beginning of the URB
  42  * space, while entries can be stored anywhere.  Ivybridge and Haswell
  43  * GT1/GT2 have a maximum constant buffer size of 16kB, while Haswell GT3
  44  * doubles this (32kB).
  45  *
  46  * Ivybridge and Haswell GT1/GT2 allow push constants to be located (and
  47  * sized) in increments of 1kB.  Haswell GT3 requires them to be located and
  48  * sized in increments of 2kB.
  49  *
  50  * Currently we split the constant buffer space evenly among whatever stages
  51  * are active.  This is probably not ideal, but simple.
  52  *
  53  * Ivybridge GT1 and Haswell GT1 have 128kB of URB space.
  54  * Ivybridge GT2 and Haswell GT2 have 256kB of URB space.
  55  * Haswell GT3 has 512kB of URB space.
  56  *
  57  * See "Volume 2a: 3D Pipeline," section 1.8, "Volume 1b: Configurations",
  58  * and the documentation for 3DSTATE_PUSH_CONSTANT_ALLOC_xS.
  59  */
  60 static void
  61 gen7_allocate_push_constants(struct brw_context *brw)
  62 {
  63    /* BRW_NEW_GEOMETRY_PROGRAM */
  64    bool gs_present = brw->geometry_program;
  65
  66    /* BRW_NEW_TESS_CTRL_PROGRAM, BRW_NEW_TESS_EVAL_PROGRAM */
  67    bool tess_present = brw->tess_eval_program;
  68
  69    unsigned avail_size = 16;
  70    unsigned multiplier =
  71       (brw->gen >= 8 || (brw->is_haswell && brw->gt == 3)) ? 2 : 1;
  72
  73    int stages = 2 + gs_present + 2 * tess_present;
  74
  75    /* Divide up the available space equally between stages.  Because we
  76     * round down (using floor division), there may be some left over
  77     * space.  We allocate that to the pixel shader stage.
  78     */
  79    unsigned size_per_stage = avail_size / stages;
  80
  81    unsigned vs_size = size_per_stage;
  82    unsigned hs_size = tess_present ? size_per_stage : 0;
  83    unsigned ds_size = tess_present ? size_per_stage : 0;
  84    unsigned gs_size = gs_present ? size_per_stage : 0;
  85    unsigned fs_size = avail_size - size_per_stage * (stages - 1);
  86
  87    gen7_emit_push_constant_state(brw, multiplier * vs_size,
  88                                  multiplier * hs_size, multiplier * ds_size,
  89                                  multiplier * gs_size, multiplier * fs_size);
  90
  91    /* From p115 of the Ivy Bridge PRM (3.2.1.4 3DSTATE_PUSH_CONSTANT_ALLOC_VS):
  92     *
  93     *     Programming Restriction:
  94     *
  95     *     The 3DSTATE_CONSTANT_VS must be reprogrammed prior to the next
  96     *     3DPRIMITIVE command after programming the
  97     *     3DSTATE_PUSH_CONSTANT_ALLOC_VS.
  98     *
  99     * Similar text exists for the other 3DSTATE_PUSH_CONSTANT_ALLOC_*
 100     * commands.
 101     */
 102    brw->ctx.NewDriverState |= BRW_NEW_PUSH_CONSTANT_ALLOCATION;
 103 }
 104
 105 void
 106 gen7_emit_push_constant_state(struct brw_context *brw, unsigned vs_size,
 107                               unsigned hs_size, unsigned ds_size,
 108                               unsigned gs_size, unsigned fs_size)
 109 {
 110    unsigned offset = 0;
 111
 112    BEGIN_BATCH(10);
 113    OUT_BATCH(_3DSTATE_PUSH_CONSTANT_ALLOC_VS << 16 | (2 - 2));
 114    OUT_BATCH(vs_size | offset << GEN7_PUSH_CONSTANT_BUFFER_OFFSET_SHIFT);
 115    offset += vs_size;
 116
 117    OUT_BATCH(_3DSTATE_PUSH_CONSTANT_ALLOC_HS << 16 | (2 - 2));
 118    OUT_BATCH(hs_size | offset << GEN7_PUSH_CONSTANT_BUFFER_OFFSET_SHIFT);
 119    offset += hs_size;
 120
 121    OUT_BATCH(_3DSTATE_PUSH_CONSTANT_ALLOC_DS << 16 | (2 - 2));
 122    OUT_BATCH(ds_size | offset << GEN7_PUSH_CONSTANT_BUFFER_OFFSET_SHIFT);
 123    offset += ds_size;
 124
 125    OUT_BATCH(_3DSTATE_PUSH_CONSTANT_ALLOC_GS << 16 | (2 - 2));
 126    OUT_BATCH(gs_size | offset << GEN7_PUSH_CONSTANT_BUFFER_OFFSET_SHIFT);
 127    offset += gs_size;
 128
 129    OUT_BATCH(_3DSTATE_PUSH_CONSTANT_ALLOC_PS << 16 | (2 - 2));
 130    OUT_BATCH(fs_size | offset << GEN7_PUSH_CONSTANT_BUFFER_OFFSET_SHIFT);
 131    ADVANCE_BATCH();
 132
 133    /* From p292 of the Ivy Bridge PRM (11.2.4 3DSTATE_PUSH_CONSTANT_ALLOC_PS):
 134     *
 135     *     A PIPE_CONTROL command with the CS Stall bit set must be programmed
 136     *     in the ring after this instruction.
 137     *
 138     * No such restriction exists for Haswell or Baytrail.
 139     */
 140    if (brw->gen < 8 && !brw->is_haswell && !brw->is_baytrail)
 141       gen7_emit_cs_stall_flush(brw);
 142 }
 143
 144 const struct brw_tracked_state gen7_push_constant_space = {
 145    .dirty = {
 146       .mesa = 0,
 147       .brw = BRW_NEW_CONTEXT |
 148              BRW_NEW_GEOMETRY_PROGRAM |
 149              BRW_NEW_TESS_CTRL_PROGRAM |
 150              BRW_NEW_TESS_EVAL_PROGRAM,
 151    },
 152    .emit = gen7_allocate_push_constants,
 153 };
 154
 155 static void
 156 gen7_upload_urb(struct brw_context *brw)
 157 {
 158    const struct brw_device_info *devinfo = brw->intelScreen->devinfo;
 159    const int push_size_kB =
 160       (brw->gen >= 8 || (brw->is_haswell && brw->gt == 3)) ? 32 : 16;
 161
 162    /* BRW_NEW_VS_PROG_DATA */
 163    unsigned vs_size = MAX2(brw->vs.prog_data->base.urb_entry_size, 1);
 164    unsigned vs_entry_size_bytes = vs_size * 64;
 165    /* BRW_NEW_GEOMETRY_PROGRAM, BRW_NEW_GS_PROG_DATA */
 166    bool gs_present = brw->geometry_program;
 167    unsigned gs_size = gs_present ? brw->gs.prog_data->base.urb_entry_size : 1;
 168    unsigned gs_entry_size_bytes = gs_size * 64;
 169
 170    /* BRW_NEW_TESS_CTRL_PROGRAM, BRW_NEW_TESS_EVAL_PROGRAM */
 171    const bool tess_present = brw->tess_eval_program;
 172    assert(!tess_present || brw->tess_ctrl_program);
 173    /* BRW_NEW_TCS_PROG_DATA */
 174    unsigned hs_size = tess_present ? brw->tcs.prog_data->base.urb_entry_size : 1;
 175    unsigned hs_entry_size_bytes = hs_size * 64;
 176    /* BRW_NEW_TES_PROG_DATA */
 177    unsigned ds_size = tess_present ? brw->tes.prog_data->base.urb_entry_size : 1;
 178    unsigned ds_entry_size_bytes = ds_size * 64;
 179
 180    /* If we're just switching between programs with the same URB requirements,
 181     * skip the rest of the logic.
 182     */
 183    if (!(brw->ctx.NewDriverState & BRW_NEW_CONTEXT) &&
 184        !(brw->ctx.NewDriverState & BRW_NEW_URB_SIZE) &&
 185        brw->urb.vsize == vs_size &&
 186        brw->urb.gs_present == gs_present &&
 187        brw->urb.gsize == gs_size &&
 188        brw->urb.tess_present == tess_present &&
 189        brw->urb.hsize == hs_size &&
 190        brw->urb.dsize == ds_size) {
 191       return;
 192    }
 193    brw->urb.vsize = vs_size;
 194    brw->urb.gs_present = gs_present;
 195    brw->urb.gsize = gs_size;
 196    brw->urb.tess_present = tess_present;
 197    brw->urb.hsize = hs_size;
 198    brw->urb.dsize = ds_size;
 199
 200    /* From p35 of the Ivy Bridge PRM (section 1.7.1: 3DSTATE_URB_GS):
 201     *
 202     *     VS Number of URB Entries must be divisible by 8 if the VS URB Entry
 203     *     Allocation Size is less than 9 512-bit URB entries.
 204     *
 205     * Similar text exists for HS, DS and GS.
 206     */
 207    unsigned vs_granularity = (vs_size < 9) ? 8 : 1;
 208    unsigned hs_granularity = (hs_size < 9) ? 8 : 1;
 209    unsigned ds_granularity = (ds_size < 9) ? 8 : 1;
 210    unsigned gs_granularity = (gs_size < 9) ? 8 : 1;
 211
 212    /* URB allocations must be done in 8k chunks. */
 213    unsigned chunk_size_bytes = 8192;
 214
 215    /* Determine the size of the URB in chunks.
 216     * BRW_NEW_URB_SIZE
 217     */
 218    unsigned urb_chunks = brw->urb.size * 1024 / chunk_size_bytes;
 219
 220    /* Reserve space for push constants */
 221    unsigned push_constant_bytes = 1024 * push_size_kB;
 222    unsigned push_constant_chunks =
 223       push_constant_bytes / chunk_size_bytes;
 224
 225    /* Initially, assign each stage the minimum amount of URB space it needs,
 226     * and make a note of how much additional space it "wants" (the amount of
 227     * additional space it could actually make use of).
 228     */
 229
 230    /* VS has a lower limit on the number of URB entries.
 231     *
 232     * From the Broadwell PRM, 3DSTATE_URB_VS instruction:
 233     * "When tessellation is enabled, the VS Number of URB Entries must be
 234     *  greater than or equal to 192."
 235     */
 236    unsigned vs_min_entries =
 237       tess_present && brw->gen == 8 ? 192 : brw->urb.min_vs_entries;
 238
 239    unsigned vs_chunks =
 240       DIV_ROUND_UP(vs_min_entries * vs_entry_size_bytes, chunk_size_bytes);
 241    unsigned vs_wants =
 242       DIV_ROUND_UP(brw->urb.max_vs_entries * vs_entry_size_bytes,
 243                    chunk_size_bytes) - vs_chunks;
 244
 245    unsigned gs_chunks = 0;
 246    unsigned gs_wants = 0;
 247    if (gs_present) {
 248       /* There are two constraints on the minimum amount of URB space we can
 249        * allocate:
 250        *
 251        * (1) We need room for at least 2 URB entries, since we always operate
 252        * the GS in DUAL_OBJECT mode.
 253        *
 254        * (2) We can't allocate less than nr_gs_entries_granularity.
 255        */
 256       gs_chunks = DIV_ROUND_UP(MAX2(gs_granularity, 2) * gs_entry_size_bytes,
 257                                chunk_size_bytes);
 258       gs_wants = DIV_ROUND_UP(brw->urb.max_gs_entries * gs_entry_size_bytes,
 259                               chunk_size_bytes) - gs_chunks;
 260    }
 261
 262    unsigned hs_chunks = 0;
 263    unsigned hs_wants = 0;
 264    unsigned ds_chunks = 0;
 265    unsigned ds_wants = 0;
 266
 267    if (tess_present) {
 268       hs_chunks =
 269          DIV_ROUND_UP(hs_granularity * hs_entry_size_bytes,
 270                       chunk_size_bytes);
 271       hs_wants =
 272          DIV_ROUND_UP(devinfo->urb.max_hs_entries * hs_entry_size_bytes,
 273                       chunk_size_bytes) - hs_chunks;
 274
 275       ds_chunks =
 276          DIV_ROUND_UP(devinfo->urb.min_ds_entries * ds_entry_size_bytes,
 277                       chunk_size_bytes);
 278       ds_wants =
 279          DIV_ROUND_UP(brw->urb.max_ds_entries * ds_entry_size_bytes,
 280                       chunk_size_bytes) - ds_chunks;
 281    }
 282
 283    /* There should always be enough URB space to satisfy the minimum
 284     * requirements of each stage.
 285     */
 286    unsigned total_needs = push_constant_chunks +
 287                           vs_chunks + hs_chunks + ds_chunks + gs_chunks;
 288    assert(total_needs <= urb_chunks);
 289
 290    /* Mete out remaining space (if any) in proportion to "wants". */
 291    unsigned total_wants = vs_wants + hs_wants + ds_wants + gs_wants;
 292    unsigned remaining_space = urb_chunks - total_needs;
 293    if (remaining_space > total_wants)
 294       remaining_space = total_wants;
 295    if (remaining_space > 0) {
 296       unsigned vs_additional = (unsigned)
 297          roundf(vs_wants * (((float) remaining_space) / total_wants));
 298       vs_chunks += vs_additional;
 299       remaining_space -= vs_additional;
 300       total_wants -= vs_wants;
 301
 302       unsigned hs_additional = (unsigned)
 303          round(hs_wants * (((double) remaining_space) / total_wants));
 304       hs_chunks += hs_additional;
 305       remaining_space -= hs_additional;
 306       total_wants -= hs_wants;
 307
 308       unsigned ds_additional = (unsigned)
 309          round(ds_wants * (((double) remaining_space) / total_wants));
 310       ds_chunks += ds_additional;
 311       remaining_space -= ds_additional;
 312       total_wants -= ds_wants;
 313
 314       gs_chunks += remaining_space;
 315    }
 316
 317    /* Sanity check that we haven't over-allocated. */
 318    assert(push_constant_chunks +
 319           vs_chunks + hs_chunks + ds_chunks + gs_chunks <= urb_chunks);
 320
 321    /* Finally, compute the number of entries that can fit in the space
 322     * allocated to each stage.
 323     */
 324    unsigned nr_vs_entries = vs_chunks * chunk_size_bytes / vs_entry_size_bytes;
 325    unsigned nr_hs_entries = hs_chunks * chunk_size_bytes / hs_entry_size_bytes;
 326    unsigned nr_ds_entries = ds_chunks * chunk_size_bytes / ds_entry_size_bytes;
 327    unsigned nr_gs_entries = gs_chunks * chunk_size_bytes / gs_entry_size_bytes;
 328
 329    /* Since we rounded up when computing *_wants, this may be slightly more
 330     * than the maximum allowed amount, so correct for that.
 331     */
 332    nr_vs_entries = MIN2(nr_vs_entries, brw->urb.max_vs_entries);
 333    nr_hs_entries = MIN2(nr_hs_entries, brw->urb.max_hs_entries);
 334    nr_ds_entries = MIN2(nr_ds_entries, brw->urb.max_ds_entries);
 335    nr_gs_entries = MIN2(nr_gs_entries, brw->urb.max_gs_entries);
 336
 337    /* Ensure that we program a multiple of the granularity. */
 338    nr_vs_entries = ROUND_DOWN_TO(nr_vs_entries, vs_granularity);
 339    nr_hs_entries = ROUND_DOWN_TO(nr_hs_entries, hs_granularity);
 340    nr_ds_entries = ROUND_DOWN_TO(nr_ds_entries, ds_granularity);
 341    nr_gs_entries = ROUND_DOWN_TO(nr_gs_entries, gs_granularity);
 342
 343    /* Finally, sanity check to make sure we have at least the minimum number
 344     * of entries needed for each stage.
 345     */
 346    assert(nr_vs_entries >= vs_min_entries);
 347    if (gs_present)
 348       assert(nr_gs_entries >= 2);
 349    if (tess_present) {
 350       assert(nr_hs_entries >= 1);
 351       assert(nr_ds_entries >= devinfo->urb.min_ds_entries);
 352    }
 353
 354    /* Gen7 doesn't actually use brw->urb.nr_{vs,gs}_entries, but it seems
 355     * better to put reasonable data in there rather than leave them
 356     * uninitialized.
 357     */
 358    brw->urb.nr_vs_entries = nr_vs_entries;
 359    brw->urb.nr_hs_entries = nr_hs_entries;
 360    brw->urb.nr_ds_entries = nr_ds_entries;
 361    brw->urb.nr_gs_entries = nr_gs_entries;
 362
 363    /* Lay out the URB in the following order:
 364     * - push constants
 365     * - VS
 366     * - HS
 367     * - DS
 368     * - GS
 369     */
 370    brw->urb.vs_start = push_constant_chunks;
 371    brw->urb.hs_start = push_constant_chunks + vs_chunks;
 372    brw->urb.ds_start = push_constant_chunks + vs_chunks + hs_chunks;
 373    brw->urb.gs_start = push_constant_chunks + vs_chunks + hs_chunks +
 374                        ds_chunks;
 375
 376    if (brw->gen == 7 && !brw->is_haswell && !brw->is_baytrail)
 377       gen7_emit_vs_workaround_flush(brw);
 378    gen7_emit_urb_state(brw,
 379                        brw->urb.nr_vs_entries, vs_size, brw->urb.vs_start,
 380                        brw->urb.nr_hs_entries, hs_size, brw->urb.hs_start,
 381                        brw->urb.nr_ds_entries, ds_size, brw->urb.ds_start,
 382                        brw->urb.nr_gs_entries, gs_size, brw->urb.gs_start);
 383 }
 384
 385 void
 386 gen7_emit_urb_state(struct brw_context *brw,
 387                     unsigned nr_vs_entries,
 388                     unsigned vs_size, unsigned vs_start,
 389                     unsigned nr_hs_entries,
 390                     unsigned hs_size, unsigned hs_start,
 391                     unsigned nr_ds_entries,
 392                     unsigned ds_size, unsigned ds_start,
 393                     unsigned nr_gs_entries,
 394                     unsigned gs_size, unsigned gs_start)
 395 {
 396    BEGIN_BATCH(8);
 397    OUT_BATCH(_3DSTATE_URB_VS << 16 | (2 - 2));
 398    OUT_BATCH(nr_vs_entries |
 399              ((vs_size - 1) << GEN7_URB_ENTRY_SIZE_SHIFT) |
 400              (vs_start << GEN7_URB_STARTING_ADDRESS_SHIFT));
 401
 402    OUT_BATCH(_3DSTATE_URB_GS << 16 | (2 - 2));
 403    OUT_BATCH(nr_gs_entries |
 404              ((gs_size - 1) << GEN7_URB_ENTRY_SIZE_SHIFT) |
 405              (gs_start << GEN7_URB_STARTING_ADDRESS_SHIFT));
 406
 407    OUT_BATCH(_3DSTATE_URB_HS << 16 | (2 - 2));
 408    OUT_BATCH(nr_hs_entries |
 409              ((hs_size - 1) << GEN7_URB_ENTRY_SIZE_SHIFT) |
 410              (hs_start << GEN7_URB_STARTING_ADDRESS_SHIFT));
 411
 412    OUT_BATCH(_3DSTATE_URB_DS << 16 | (2 - 2));
 413    OUT_BATCH(nr_ds_entries |
 414              ((ds_size - 1) << GEN7_URB_ENTRY_SIZE_SHIFT) |
 415              (ds_start << GEN7_URB_STARTING_ADDRESS_SHIFT));
 416    ADVANCE_BATCH();
 417 }
 418
 419 const struct brw_tracked_state gen7_urb = {
 420    .dirty = {
 421       .mesa = 0,
 422       .brw = BRW_NEW_CONTEXT |
 423              BRW_NEW_URB_SIZE |
 424              BRW_NEW_GEOMETRY_PROGRAM |
 425              BRW_NEW_TESS_CTRL_PROGRAM |
 426              BRW_NEW_TESS_EVAL_PROGRAM |
 427              BRW_NEW_GS_PROG_DATA |
 428              BRW_NEW_TCS_PROG_DATA |
 429              BRW_NEW_TES_PROG_DATA |
 430              BRW_NEW_VS_PROG_DATA,
 431    },
 432    .emit = gen7_upload_urb,
 433 };