src/mesa/drivers/dri/i965/gen7_urb.c

   1 /*
   2  * Copyright © 2011 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include "main/macros.h"
  25 #include "intel_batchbuffer.h"
  26 #include "brw_context.h"
  27 #include "brw_state.h"
  28 #include "brw_defines.h"
  29
  30 /**
  31  * The following diagram shows how we partition the URB:
  32  *
  33  *        16kB or 32kB               Rest of the URB space
  34  *   __________-__________   _________________-_________________
  35  *  /                     \ /                                   \
  36  * +-------------------------------------------------------------+
  37  * |  VS/HS/DS/GS/FS Push  |           VS/HS/DS/GS URB           |
  38  * |       Constants       |               Entries               |
  39  * +-------------------------------------------------------------+
  40  *
  41  * Notably, push constants must be stored at the beginning of the URB
  42  * space, while entries can be stored anywhere.  Ivybridge and Haswell
  43  * GT1/GT2 have a maximum constant buffer size of 16kB, while Haswell GT3
  44  * doubles this (32kB).
  45  *
  46  * Ivybridge and Haswell GT1/GT2 allow push constants to be located (and
  47  * sized) in increments of 1kB.  Haswell GT3 requires them to be located and
  48  * sized in increments of 2kB.
  49  *
  50  * Currently we split the constant buffer space evenly among whatever stages
  51  * are active.  This is probably not ideal, but simple.
  52  *
  53  * Ivybridge GT1 and Haswell GT1 have 128kB of URB space.
  54  * Ivybridge GT2 and Haswell GT2 have 256kB of URB space.
  55  * Haswell GT3 has 512kB of URB space.
  56  *
  57  * See "Volume 2a: 3D Pipeline," section 1.8, "Volume 1b: Configurations",
  58  * and the documentation for 3DSTATE_PUSH_CONSTANT_ALLOC_xS.
  59  */
  60 static void
  61 gen7_allocate_push_constants(struct brw_context *brw)
  62 {
  63    /* BRW_NEW_GEOMETRY_PROGRAM */
  64    bool gs_present = brw->geometry_program;
  65
  66    /* BRW_NEW_TESS_PROGRAMS */
  67    bool tess_present = brw->tess_eval_program;
  68
  69    unsigned avail_size = 16;
  70    unsigned multiplier =
  71       (brw->gen >= 8 || (brw->is_haswell && brw->gt == 3)) ? 2 : 1;
  72
  73    int stages = 2 + gs_present + 2 * tess_present;
  74
  75    /* Divide up the available space equally between stages.  Because we
  76     * round down (using floor division), there may be some left over
  77     * space.  We allocate that to the pixel shader stage.
  78     */
  79    unsigned size_per_stage = avail_size / stages;
  80
  81    unsigned vs_size = size_per_stage;
  82    unsigned hs_size = tess_present ? size_per_stage : 0;
  83    unsigned ds_size = tess_present ? size_per_stage : 0;
  84    unsigned gs_size = gs_present ? size_per_stage : 0;
  85    unsigned fs_size = avail_size - size_per_stage * (stages - 1);
  86
  87    gen7_emit_push_constant_state(brw, multiplier * vs_size,
  88                                  multiplier * hs_size, multiplier * ds_size,
  89                                  multiplier * gs_size, multiplier * fs_size);
  90
  91    /* From p115 of the Ivy Bridge PRM (3.2.1.4 3DSTATE_PUSH_CONSTANT_ALLOC_VS):
  92     *
  93     *     Programming Restriction:
  94     *
  95     *     The 3DSTATE_CONSTANT_VS must be reprogrammed prior to the next
  96     *     3DPRIMITIVE command after programming the
  97     *     3DSTATE_PUSH_CONSTANT_ALLOC_VS.
  98     *
  99     * Similar text exists for the other 3DSTATE_PUSH_CONSTANT_ALLOC_*
 100     * commands.
 101     */
 102    brw->ctx.NewDriverState |= BRW_NEW_PUSH_CONSTANT_ALLOCATION;
 103 }
 104
 105 void
 106 gen7_emit_push_constant_state(struct brw_context *brw, unsigned vs_size,
 107                               unsigned hs_size, unsigned ds_size,
 108                               unsigned gs_size, unsigned fs_size)
 109 {
 110    unsigned offset = 0;
 111
 112    BEGIN_BATCH(10);
 113    OUT_BATCH(_3DSTATE_PUSH_CONSTANT_ALLOC_VS << 16 | (2 - 2));
 114    OUT_BATCH(vs_size | offset << GEN7_PUSH_CONSTANT_BUFFER_OFFSET_SHIFT);
 115    offset += vs_size;
 116
 117    OUT_BATCH(_3DSTATE_PUSH_CONSTANT_ALLOC_HS << 16 | (2 - 2));
 118    OUT_BATCH(hs_size | offset << GEN7_PUSH_CONSTANT_BUFFER_OFFSET_SHIFT);
 119    offset += hs_size;
 120
 121    OUT_BATCH(_3DSTATE_PUSH_CONSTANT_ALLOC_DS << 16 | (2 - 2));
 122    OUT_BATCH(ds_size | offset << GEN7_PUSH_CONSTANT_BUFFER_OFFSET_SHIFT);
 123    offset += ds_size;
 124
 125    OUT_BATCH(_3DSTATE_PUSH_CONSTANT_ALLOC_GS << 16 | (2 - 2));
 126    OUT_BATCH(gs_size | offset << GEN7_PUSH_CONSTANT_BUFFER_OFFSET_SHIFT);
 127    offset += gs_size;
 128
 129    OUT_BATCH(_3DSTATE_PUSH_CONSTANT_ALLOC_PS << 16 | (2 - 2));
 130    OUT_BATCH(fs_size | offset << GEN7_PUSH_CONSTANT_BUFFER_OFFSET_SHIFT);
 131    ADVANCE_BATCH();
 132
 133    /* From p292 of the Ivy Bridge PRM (11.2.4 3DSTATE_PUSH_CONSTANT_ALLOC_PS):
 134     *
 135     *     A PIPE_CONTROL command with the CS Stall bit set must be programmed
 136     *     in the ring after this instruction.
 137     *
 138     * No such restriction exists for Haswell or Baytrail.
 139     */
 140    if (brw->gen < 8 && !brw->is_haswell && !brw->is_baytrail)
 141       gen7_emit_cs_stall_flush(brw);
 142 }
 143
 144 const struct brw_tracked_state gen7_push_constant_space = {
 145    .dirty = {
 146       .mesa = 0,
 147       .brw = BRW_NEW_CONTEXT |
 148              BRW_NEW_GEOMETRY_PROGRAM |
 149              BRW_NEW_TESS_PROGRAMS,
 150    },
 151    .emit = gen7_allocate_push_constants,
 152 };
 153
 154 static void
 155 gen7_emit_urb_state(struct brw_context *brw,
 156                     unsigned nr_vs_entries,
 157                     unsigned vs_size, unsigned vs_start,
 158                     unsigned nr_hs_entries,
 159                     unsigned hs_size, unsigned hs_start,
 160                     unsigned nr_ds_entries,
 161                     unsigned ds_size, unsigned ds_start,
 162                     unsigned nr_gs_entries,
 163                     unsigned gs_size, unsigned gs_start)
 164 {
 165    BEGIN_BATCH(8);
 166    OUT_BATCH(_3DSTATE_URB_VS << 16 | (2 - 2));
 167    OUT_BATCH(nr_vs_entries |
 168              ((vs_size - 1) << GEN7_URB_ENTRY_SIZE_SHIFT) |
 169              (vs_start << GEN7_URB_STARTING_ADDRESS_SHIFT));
 170
 171    OUT_BATCH(_3DSTATE_URB_GS << 16 | (2 - 2));
 172    OUT_BATCH(nr_gs_entries |
 173              ((gs_size - 1) << GEN7_URB_ENTRY_SIZE_SHIFT) |
 174              (gs_start << GEN7_URB_STARTING_ADDRESS_SHIFT));
 175
 176    OUT_BATCH(_3DSTATE_URB_HS << 16 | (2 - 2));
 177    OUT_BATCH(nr_hs_entries |
 178              ((hs_size - 1) << GEN7_URB_ENTRY_SIZE_SHIFT) |
 179              (hs_start << GEN7_URB_STARTING_ADDRESS_SHIFT));
 180
 181    OUT_BATCH(_3DSTATE_URB_DS << 16 | (2 - 2));
 182    OUT_BATCH(nr_ds_entries |
 183              ((ds_size - 1) << GEN7_URB_ENTRY_SIZE_SHIFT) |
 184              (ds_start << GEN7_URB_STARTING_ADDRESS_SHIFT));
 185    ADVANCE_BATCH();
 186 }
 187
 188 static void
 189 upload_urb(struct brw_context *brw)
 190 {
 191    /* BRW_NEW_VS_PROG_DATA */
 192    const struct brw_vue_prog_data *vs_vue_prog_data =
 193       brw_vue_prog_data(brw->vs.base.prog_data);
 194    const unsigned vs_size = MAX2(vs_vue_prog_data->urb_entry_size, 1);
 195    /* BRW_NEW_GS_PROG_DATA */
 196    const bool gs_present = brw->gs.base.prog_data;
 197    /* BRW_NEW_TES_PROG_DATA */
 198    const bool tess_present = brw->tes.base.prog_data;
 199
 200    gen7_upload_urb(brw, vs_size, gs_present, tess_present);
 201 }
 202
 203 void
 204 gen7_upload_urb(struct brw_context *brw, unsigned vs_size,
 205                 bool gs_present, bool tess_present)
 206 {
 207    const struct gen_device_info *devinfo = &brw->screen->devinfo;
 208    const int push_size_kB =
 209       (brw->gen >= 8 || (brw->is_haswell && brw->gt == 3)) ? 32 : 16;
 210
 211    /* BRW_NEW_VS_PROG_DATA */
 212    unsigned vs_entry_size_bytes = vs_size * 64;
 213    /* BRW_NEW_GEOMETRY_PROGRAM, BRW_NEW_GS_PROG_DATA */
 214    const struct brw_vue_prog_data *gs_vue_prog_data =
 215       brw_vue_prog_data(brw->gs.base.prog_data);
 216    unsigned gs_size = gs_present ? gs_vue_prog_data->urb_entry_size : 1;
 217    unsigned gs_entry_size_bytes = gs_size * 64;
 218
 219    /* BRW_NEW_TCS_PROG_DATA */
 220    const struct brw_vue_prog_data *tcs_vue_prog_data =
 221       brw_vue_prog_data(brw->tcs.base.prog_data);
 222    unsigned hs_size = tess_present ? tcs_vue_prog_data->urb_entry_size : 1;
 223    unsigned hs_entry_size_bytes = hs_size * 64;
 224    /* BRW_NEW_TES_PROG_DATA */
 225    const struct brw_vue_prog_data *tes_vue_prog_data =
 226       brw_vue_prog_data(brw->tes.base.prog_data);
 227    unsigned ds_size = tess_present ? tes_vue_prog_data->urb_entry_size : 1;
 228    unsigned ds_entry_size_bytes = ds_size * 64;
 229
 230    /* If we're just switching between programs with the same URB requirements,
 231     * skip the rest of the logic.
 232     */
 233    if (!(brw->ctx.NewDriverState & BRW_NEW_CONTEXT) &&
 234        !(brw->ctx.NewDriverState & BRW_NEW_URB_SIZE) &&
 235        brw->urb.vsize == vs_size &&
 236        brw->urb.gs_present == gs_present &&
 237        brw->urb.gsize == gs_size &&
 238        brw->urb.tess_present == tess_present &&
 239        brw->urb.hsize == hs_size &&
 240        brw->urb.dsize == ds_size) {
 241       return;
 242    }
 243    brw->urb.vsize = vs_size;
 244    brw->urb.gs_present = gs_present;
 245    brw->urb.gsize = gs_size;
 246    brw->urb.tess_present = tess_present;
 247    brw->urb.hsize = hs_size;
 248    brw->urb.dsize = ds_size;
 249
 250    /* From p35 of the Ivy Bridge PRM (section 1.7.1: 3DSTATE_URB_GS):
 251     *
 252     *     VS Number of URB Entries must be divisible by 8 if the VS URB Entry
 253     *     Allocation Size is less than 9 512-bit URB entries.
 254     *
 255     * Similar text exists for HS, DS and GS.
 256     */
 257    unsigned vs_granularity = (vs_size < 9) ? 8 : 1;
 258    unsigned hs_granularity = (hs_size < 9) ? 8 : 1;
 259    unsigned ds_granularity = (ds_size < 9) ? 8 : 1;
 260    unsigned gs_granularity = (gs_size < 9) ? 8 : 1;
 261
 262    /* URB allocations must be done in 8k chunks. */
 263    unsigned chunk_size_bytes = 8192;
 264
 265    /* Determine the size of the URB in chunks.
 266     * BRW_NEW_URB_SIZE
 267     */
 268    unsigned urb_chunks = brw->urb.size * 1024 / chunk_size_bytes;
 269
 270    /* Reserve space for push constants */
 271    unsigned push_constant_bytes = 1024 * push_size_kB;
 272    unsigned push_constant_chunks =
 273       push_constant_bytes / chunk_size_bytes;
 274
 275    /* Initially, assign each stage the minimum amount of URB space it needs,
 276     * and make a note of how much additional space it "wants" (the amount of
 277     * additional space it could actually make use of).
 278     */
 279
 280    /* VS has a lower limit on the number of URB entries.
 281     *
 282     * From the Broadwell PRM, 3DSTATE_URB_VS instruction:
 283     * "When tessellation is enabled, the VS Number of URB Entries must be
 284     *  greater than or equal to 192."
 285     */
 286    unsigned vs_min_entries =
 287       tess_present && brw->gen == 8 ?
 288          192 : devinfo->urb.min_entries[MESA_SHADER_VERTEX];
 289    /* Min VS Entries isn't a multiple of 8 on Cherryview/Broxton; round up */
 290    vs_min_entries = ALIGN(vs_min_entries, vs_granularity);
 291
 292    unsigned vs_chunks =
 293       DIV_ROUND_UP(vs_min_entries * vs_entry_size_bytes, chunk_size_bytes);
 294    unsigned vs_wants =
 295       DIV_ROUND_UP(devinfo->urb.max_entries[MESA_SHADER_VERTEX] *
 296                    vs_entry_size_bytes,
 297                    chunk_size_bytes) - vs_chunks;
 298
 299    unsigned gs_chunks = 0;
 300    unsigned gs_wants = 0;
 301    if (gs_present) {
 302       /* There are two constraints on the minimum amount of URB space we can
 303        * allocate:
 304        *
 305        * (1) We need room for at least 2 URB entries, since we always operate
 306        * the GS in DUAL_OBJECT mode.
 307        *
 308        * (2) We can't allocate less than nr_gs_entries_granularity.
 309        */
 310       gs_chunks = DIV_ROUND_UP(MAX2(gs_granularity, 2) * gs_entry_size_bytes,
 311                                chunk_size_bytes);
 312       gs_wants = DIV_ROUND_UP(devinfo->urb.max_entries[MESA_SHADER_GEOMETRY] *
 313                               gs_entry_size_bytes,
 314                               chunk_size_bytes) - gs_chunks;
 315    }
 316
 317    unsigned hs_chunks = 0;
 318    unsigned hs_wants = 0;
 319    unsigned ds_chunks = 0;
 320    unsigned ds_wants = 0;
 321
 322    if (tess_present) {
 323       hs_chunks =
 324          DIV_ROUND_UP(hs_granularity * hs_entry_size_bytes,
 325                       chunk_size_bytes);
 326       hs_wants =
 327          DIV_ROUND_UP(devinfo->urb.max_entries[MESA_SHADER_TESS_CTRL] *
 328                       hs_entry_size_bytes, chunk_size_bytes) - hs_chunks;
 329
 330       ds_chunks =
 331          DIV_ROUND_UP(devinfo->urb.min_entries[MESA_SHADER_TESS_EVAL] *
 332                       ds_entry_size_bytes, chunk_size_bytes);
 333       ds_wants =
 334          DIV_ROUND_UP(devinfo->urb.max_entries[MESA_SHADER_TESS_EVAL] *
 335                       ds_entry_size_bytes, chunk_size_bytes) - ds_chunks;
 336    }
 337
 338    /* There should always be enough URB space to satisfy the minimum
 339     * requirements of each stage.
 340     */
 341    unsigned total_needs = push_constant_chunks +
 342                           vs_chunks + hs_chunks + ds_chunks + gs_chunks;
 343    assert(total_needs <= urb_chunks);
 344
 345    /* Mete out remaining space (if any) in proportion to "wants". */
 346    unsigned total_wants = vs_wants + hs_wants + ds_wants + gs_wants;
 347    unsigned remaining_space = urb_chunks - total_needs;
 348    if (remaining_space > total_wants)
 349       remaining_space = total_wants;
 350    if (remaining_space > 0) {
 351       unsigned vs_additional = (unsigned)
 352          roundf(vs_wants * (((float) remaining_space) / total_wants));
 353       vs_chunks += vs_additional;
 354       remaining_space -= vs_additional;
 355       total_wants -= vs_wants;
 356
 357       if (total_wants > 0) {
 358          unsigned hs_additional = (unsigned)
 359             roundf(hs_wants * (((float) remaining_space) / total_wants));
 360          hs_chunks += hs_additional;
 361          remaining_space -= hs_additional;
 362          total_wants -= hs_wants;
 363       }
 364
 365       if (total_wants > 0) {
 366          unsigned ds_additional = (unsigned)
 367             roundf(ds_wants * (((float) remaining_space) / total_wants));
 368          ds_chunks += ds_additional;
 369          remaining_space -= ds_additional;
 370          total_wants -= ds_wants;
 371       }
 372
 373       gs_chunks += remaining_space;
 374    }
 375
 376    /* Sanity check that we haven't over-allocated. */
 377    assert(push_constant_chunks +
 378           vs_chunks + hs_chunks + ds_chunks + gs_chunks <= urb_chunks);
 379
 380    /* Finally, compute the number of entries that can fit in the space
 381     * allocated to each stage.
 382     */
 383    unsigned nr_vs_entries = vs_chunks * chunk_size_bytes / vs_entry_size_bytes;
 384    unsigned nr_hs_entries = hs_chunks * chunk_size_bytes / hs_entry_size_bytes;
 385    unsigned nr_ds_entries = ds_chunks * chunk_size_bytes / ds_entry_size_bytes;
 386    unsigned nr_gs_entries = gs_chunks * chunk_size_bytes / gs_entry_size_bytes;
 387
 388    /* Since we rounded up when computing *_wants, this may be slightly more
 389     * than the maximum allowed amount, so correct for that.
 390     */
 391    nr_vs_entries =
 392       MIN2(nr_vs_entries, devinfo->urb.max_entries[MESA_SHADER_VERTEX]);
 393    nr_hs_entries =
 394       MIN2(nr_hs_entries, devinfo->urb.max_entries[MESA_SHADER_TESS_CTRL]);
 395    nr_ds_entries =
 396       MIN2(nr_ds_entries, devinfo->urb.max_entries[MESA_SHADER_TESS_EVAL]);
 397    nr_gs_entries =
 398       MIN2(nr_gs_entries, devinfo->urb.max_entries[MESA_SHADER_GEOMETRY]);
 399
 400    /* Ensure that we program a multiple of the granularity. */
 401    nr_vs_entries = ROUND_DOWN_TO(nr_vs_entries, vs_granularity);
 402    nr_hs_entries = ROUND_DOWN_TO(nr_hs_entries, hs_granularity);
 403    nr_ds_entries = ROUND_DOWN_TO(nr_ds_entries, ds_granularity);
 404    nr_gs_entries = ROUND_DOWN_TO(nr_gs_entries, gs_granularity);
 405
 406    /* Finally, sanity check to make sure we have at least the minimum number
 407     * of entries needed for each stage.
 408     */
 409    assert(nr_vs_entries >= vs_min_entries);
 410    if (gs_present)
 411       assert(nr_gs_entries >= 2);
 412    if (tess_present) {
 413       assert(nr_hs_entries >= 1);
 414       assert(nr_ds_entries >= devinfo->urb.min_entries[MESA_SHADER_TESS_EVAL]);
 415    }
 416
 417    /* Lay out the URB in the following order:
 418     * - push constants
 419     * - VS
 420     * - HS
 421     * - DS
 422     * - GS
 423     */
 424    unsigned vs_start = push_constant_chunks;
 425    unsigned hs_start = push_constant_chunks + vs_chunks;
 426    unsigned ds_start = push_constant_chunks + vs_chunks + hs_chunks;
 427    unsigned gs_start = push_constant_chunks + vs_chunks + hs_chunks +
 428                        ds_chunks;
 429
 430    if (brw->gen == 7 && !brw->is_haswell && !brw->is_baytrail)
 431       gen7_emit_vs_workaround_flush(brw);
 432    gen7_emit_urb_state(brw,
 433                        nr_vs_entries, vs_size, vs_start,
 434                        nr_hs_entries, hs_size, hs_start,
 435                        nr_ds_entries, ds_size, ds_start,
 436                        nr_gs_entries, gs_size, gs_start);
 437 }
 438
 439 const struct brw_tracked_state gen7_urb = {
 440    .dirty = {
 441       .mesa = 0,
 442       .brw = BRW_NEW_CONTEXT |
 443              BRW_NEW_URB_SIZE |
 444              BRW_NEW_GS_PROG_DATA |
 445              BRW_NEW_TCS_PROG_DATA |
 446              BRW_NEW_TES_PROG_DATA |
 447              BRW_NEW_VS_PROG_DATA,
 448    },
 449    .emit = upload_urb,
 450 };