2 * Copyright © 2011 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 #include "brw_context.h"
25 #include "brw_state.h"
26 #include "brw_defines.h"
28 #include "program/prog_parameter.h"
29 #include "program/prog_statevars.h"
30 #include "intel_batchbuffer.h"
34 gen7_upload_constant_state(struct brw_context
*brw
,
35 const struct brw_stage_state
*stage_state
,
36 bool active
, unsigned opcode
)
38 uint32_t mocs
= brw
->gen
< 8 ? GEN7_MOCS_L3
: 0;
40 /* Disable if the shader stage is inactive or there are no push constants. */
41 active
= active
&& stage_state
->push_const_size
!= 0;
43 int dwords
= brw
->gen
>= 8 ? 11 : 7;
45 OUT_BATCH(opcode
<< 16 | (dwords
- 2));
46 OUT_BATCH(active
? stage_state
->push_const_size
: 0);
48 /* Pointer to the constant buffer. Covered by the set of state flags
49 * from gen6_prepare_wm_contants
51 OUT_BATCH(active
? (stage_state
->push_const_offset
| mocs
) : 0);
64 /* On SKL+ the new constants don't take effect until the next corresponding
65 * 3DSTATE_BINDING_TABLE_POINTER_* command is parsed so we need to ensure
69 brw
->ctx
.NewDriverState
|= BRW_NEW_SURFACES
;
74 upload_vs_state(struct brw_context
*brw
)
76 const struct brw_stage_state
*stage_state
= &brw
->vs
.base
;
77 uint32_t floating_point_mode
= 0;
78 const int max_threads_shift
= brw
->is_haswell
?
79 HSW_VS_MAX_THREADS_SHIFT
: GEN6_VS_MAX_THREADS_SHIFT
;
81 if (!brw
->is_haswell
&& !brw
->is_baytrail
)
82 gen7_emit_vs_workaround_flush(brw
);
84 if (brw
->vs
.prog_data
->base
.base
.use_alt_mode
)
85 floating_point_mode
= GEN6_VS_FLOATING_POINT_MODE_ALT
;
88 OUT_BATCH(_3DSTATE_VS
<< 16 | (6 - 2));
89 OUT_BATCH(stage_state
->prog_offset
);
90 OUT_BATCH(floating_point_mode
|
91 ((ALIGN(stage_state
->sampler_count
, 4)/4) <<
92 GEN6_VS_SAMPLER_COUNT_SHIFT
) |
93 ((brw
->vs
.prog_data
->base
.base
.binding_table
.size_bytes
/ 4) <<
94 GEN6_VS_BINDING_TABLE_ENTRY_COUNT_SHIFT
));
96 if (brw
->vs
.prog_data
->base
.base
.total_scratch
) {
97 OUT_RELOC(stage_state
->scratch_bo
,
98 I915_GEM_DOMAIN_RENDER
, I915_GEM_DOMAIN_RENDER
,
99 ffs(brw
->vs
.prog_data
->base
.base
.total_scratch
) - 11);
104 OUT_BATCH((brw
->vs
.prog_data
->base
.base
.dispatch_grf_start_reg
<<
105 GEN6_VS_DISPATCH_START_GRF_SHIFT
) |
106 (brw
->vs
.prog_data
->base
.urb_read_length
<< GEN6_VS_URB_READ_LENGTH_SHIFT
) |
107 (0 << GEN6_VS_URB_ENTRY_READ_OFFSET_SHIFT
));
109 OUT_BATCH(((brw
->max_vs_threads
- 1) << max_threads_shift
) |
110 GEN6_VS_STATISTICS_ENABLE
|
115 const struct brw_tracked_state gen7_vs_state
= {
117 .mesa
= _NEW_TRANSFORM
,
118 .brw
= BRW_NEW_BATCH
|
120 BRW_NEW_VS_PROG_DATA
,
122 .emit
= upload_vs_state
,