src/mesa/drivers/dri/i965/gen7_vs_state.c

   1 /*
   2  * Copyright © 2011 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include "brw_context.h"
  25 #include "brw_state.h"
  26 #include "brw_defines.h"
  27 #include "brw_util.h"
  28 #include "program/prog_parameter.h"
  29 #include "program/prog_statevars.h"
  30 #include "intel_batchbuffer.h"
  31
  32
  33 void
  34 gen7_upload_constant_state(struct brw_context *brw,
  35                            const struct brw_stage_state *stage_state,
  36                            bool active, unsigned opcode)
  37 {
  38    uint32_t mocs = brw->gen < 8 ? GEN7_MOCS_L3 : 0;
  39
  40    /* Disable if the shader stage is inactive or there are no push constants. */
  41    active = active && stage_state->push_const_size != 0;
  42
  43    int dwords = brw->gen >= 8 ? 11 : 7;
  44    BEGIN_BATCH(dwords);
  45    OUT_BATCH(opcode << 16 | (dwords - 2));
  46    OUT_BATCH(active ? stage_state->push_const_size : 0);
  47    OUT_BATCH(0);
  48    /* Pointer to the constant buffer.  Covered by the set of state flags
  49     * from gen6_prepare_wm_contants
  50     */
  51    OUT_BATCH(active ? (stage_state->push_const_offset | mocs) : 0);
  52    OUT_BATCH(0);
  53    OUT_BATCH(0);
  54    OUT_BATCH(0);
  55    if (brw->gen >= 8) {
  56       OUT_BATCH(0);
  57       OUT_BATCH(0);
  58       OUT_BATCH(0);
  59       OUT_BATCH(0);
  60    }
  61
  62    ADVANCE_BATCH();
  63 }
  64
  65
  66 static void
  67 upload_vs_state(struct brw_context *brw)
  68 {
  69    const struct brw_stage_state *stage_state = &brw->vs.base;
  70    uint32_t floating_point_mode = 0;
  71    const int max_threads_shift = brw->is_haswell ?
  72       HSW_VS_MAX_THREADS_SHIFT : GEN6_VS_MAX_THREADS_SHIFT;
  73
  74    if (!brw->is_haswell && !brw->is_baytrail)
  75       gen7_emit_vs_workaround_flush(brw);
  76
  77    if (brw->vs.prog_data->base.base.use_alt_mode)
  78       floating_point_mode = GEN6_VS_FLOATING_POINT_MODE_ALT;
  79
  80    BEGIN_BATCH(6);
  81    OUT_BATCH(_3DSTATE_VS << 16 | (6 - 2));
  82    OUT_BATCH(stage_state->prog_offset);
  83    OUT_BATCH(floating_point_mode |
  84              ((ALIGN(stage_state->sampler_count, 4)/4) <<
  85               GEN6_VS_SAMPLER_COUNT_SHIFT) |
  86              ((brw->vs.prog_data->base.base.binding_table.size_bytes / 4) <<
  87               GEN6_VS_BINDING_TABLE_ENTRY_COUNT_SHIFT));
  88
  89    if (brw->vs.prog_data->base.base.total_scratch) {
  90       OUT_RELOC(stage_state->scratch_bo,
  91                 I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
  92                 ffs(brw->vs.prog_data->base.base.total_scratch) - 11);
  93    } else {
  94       OUT_BATCH(0);
  95    }
  96
  97    OUT_BATCH((brw->vs.prog_data->base.base.dispatch_grf_start_reg <<
  98               GEN6_VS_DISPATCH_START_GRF_SHIFT) |
  99              (brw->vs.prog_data->base.urb_read_length << GEN6_VS_URB_READ_LENGTH_SHIFT) |
 100              (0 << GEN6_VS_URB_ENTRY_READ_OFFSET_SHIFT));
 101
 102    OUT_BATCH(((brw->max_vs_threads - 1) << max_threads_shift) |
 103              GEN6_VS_STATISTICS_ENABLE |
 104              GEN6_VS_ENABLE);
 105    ADVANCE_BATCH();
 106 }
 107
 108 const struct brw_tracked_state gen7_vs_state = {
 109    .dirty = {
 110       .mesa  = _NEW_TRANSFORM,
 111       .brw   = BRW_NEW_BATCH |
 112                BRW_NEW_CONTEXT |
 113                BRW_NEW_VS_PROG_DATA,
 114    },
 115    .emit = upload_vs_state,
 116 };