i965: Add HiZ operation state to brw_context
[mesa.git] / src / mesa / drivers / dri / i965 / gen7_vs_state.c
1 /*
2 * Copyright © 2011 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include "brw_context.h"
25 #include "brw_state.h"
26 #include "brw_defines.h"
27 #include "brw_util.h"
28 #include "program/prog_parameter.h"
29 #include "program/prog_statevars.h"
30 #include "intel_batchbuffer.h"
31
32 static void
33 upload_vs_state(struct brw_context *brw)
34 {
35 struct intel_context *intel = &brw->intel;
36 uint32_t floating_point_mode = 0;
37
38 BEGIN_BATCH(2);
39 OUT_BATCH(_3DSTATE_BINDING_TABLE_POINTERS_VS << 16 | (2 - 2));
40 OUT_BATCH(brw->bind.bo_offset);
41 ADVANCE_BATCH();
42
43 /* CACHE_NEW_SAMPLER */
44 BEGIN_BATCH(2);
45 OUT_BATCH(_3DSTATE_SAMPLER_STATE_POINTERS_VS << 16 | (2 - 2));
46 OUT_BATCH(brw->sampler.offset);
47 ADVANCE_BATCH();
48
49 if (brw->vs.push_const_size == 0) {
50 /* Disable the push constant buffers. */
51 BEGIN_BATCH(7);
52 OUT_BATCH(_3DSTATE_CONSTANT_VS << 16 | (7 - 2));
53 OUT_BATCH(0);
54 OUT_BATCH(0);
55 OUT_BATCH(0);
56 OUT_BATCH(0);
57 OUT_BATCH(0);
58 OUT_BATCH(0);
59 ADVANCE_BATCH();
60 } else {
61 BEGIN_BATCH(7);
62 OUT_BATCH(_3DSTATE_CONSTANT_VS << 16 | (7 - 2));
63 OUT_BATCH(brw->vs.push_const_size);
64 OUT_BATCH(0);
65 /* Pointer to the VS constant buffer. Covered by the set of
66 * state flags from gen6_prepare_wm_contants
67 */
68 OUT_BATCH(brw->vs.push_const_offset);
69 OUT_BATCH(0);
70 OUT_BATCH(0);
71 OUT_BATCH(0);
72 ADVANCE_BATCH();
73 }
74
75 /* Use ALT floating point mode for ARB vertex programs, because they
76 * require 0^0 == 1.
77 */
78 if (intel->ctx.Shader.CurrentVertexProgram == NULL)
79 floating_point_mode = GEN6_VS_FLOATING_POINT_MODE_ALT;
80
81 BEGIN_BATCH(6);
82 OUT_BATCH(_3DSTATE_VS << 16 | (6 - 2));
83 OUT_BATCH(brw->vs.prog_offset);
84 OUT_BATCH(floating_point_mode |
85 ((ALIGN(brw->sampler.count, 4)/4) << GEN6_VS_SAMPLER_COUNT_SHIFT));
86
87 if (brw->vs.prog_data->total_scratch) {
88 OUT_RELOC(brw->vs.scratch_bo,
89 I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
90 ffs(brw->vs.prog_data->total_scratch) - 11);
91 } else {
92 OUT_BATCH(0);
93 }
94
95 OUT_BATCH((1 << GEN6_VS_DISPATCH_START_GRF_SHIFT) |
96 (brw->vs.prog_data->urb_read_length << GEN6_VS_URB_READ_LENGTH_SHIFT) |
97 (0 << GEN6_VS_URB_ENTRY_READ_OFFSET_SHIFT));
98
99 OUT_BATCH(((brw->max_vs_threads - 1) << GEN6_VS_MAX_THREADS_SHIFT) |
100 GEN6_VS_STATISTICS_ENABLE |
101 GEN6_VS_ENABLE);
102 ADVANCE_BATCH();
103 }
104
105 const struct brw_tracked_state gen7_vs_state = {
106 .dirty = {
107 .mesa = _NEW_TRANSFORM | _NEW_PROGRAM_CONSTANTS,
108 .brw = (BRW_NEW_CURBE_OFFSETS |
109 BRW_NEW_URB_FENCE |
110 BRW_NEW_CONTEXT |
111 BRW_NEW_VERTEX_PROGRAM |
112 BRW_NEW_VS_BINDING_TABLE |
113 BRW_NEW_BATCH),
114 .cache = CACHE_NEW_VS_PROG | CACHE_NEW_SAMPLER
115 },
116 .emit = upload_vs_state,
117 };