73822e3350c5eaef4e6c7b72f7a930c83e57180f
[mesa.git] / src / mesa / drivers / dri / i965 / gen7_vs_state.c
1 /*
2 * Copyright © 2011 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include "brw_context.h"
25 #include "brw_state.h"
26 #include "brw_defines.h"
27 #include "brw_util.h"
28 #include "program/prog_parameter.h"
29 #include "program/prog_statevars.h"
30 #include "intel_batchbuffer.h"
31
32 static void
33 upload_vs_state(struct brw_context *brw)
34 {
35 struct intel_context *intel = &brw->intel;
36 uint32_t floating_point_mode = 0;
37
38 gen7_emit_vs_workaround_flush(intel);
39
40 /* BRW_NEW_VS_BINDING_TABLE */
41 BEGIN_BATCH(2);
42 OUT_BATCH(_3DSTATE_BINDING_TABLE_POINTERS_VS << 16 | (2 - 2));
43 OUT_BATCH(brw->vs.bind_bo_offset);
44 ADVANCE_BATCH();
45
46 /* CACHE_NEW_SAMPLER */
47 BEGIN_BATCH(2);
48 OUT_BATCH(_3DSTATE_SAMPLER_STATE_POINTERS_VS << 16 | (2 - 2));
49 OUT_BATCH(brw->sampler.offset);
50 ADVANCE_BATCH();
51
52 if (brw->vs.push_const_size == 0) {
53 /* Disable the push constant buffers. */
54 BEGIN_BATCH(7);
55 OUT_BATCH(_3DSTATE_CONSTANT_VS << 16 | (7 - 2));
56 OUT_BATCH(0);
57 OUT_BATCH(0);
58 OUT_BATCH(0);
59 OUT_BATCH(0);
60 OUT_BATCH(0);
61 OUT_BATCH(0);
62 ADVANCE_BATCH();
63 } else {
64 BEGIN_BATCH(7);
65 OUT_BATCH(_3DSTATE_CONSTANT_VS << 16 | (7 - 2));
66 OUT_BATCH(brw->vs.push_const_size);
67 OUT_BATCH(0);
68 /* Pointer to the VS constant buffer. Covered by the set of
69 * state flags from gen6_prepare_wm_contants
70 */
71 OUT_BATCH(brw->vs.push_const_offset);
72 OUT_BATCH(0);
73 OUT_BATCH(0);
74 OUT_BATCH(0);
75 ADVANCE_BATCH();
76 }
77
78 /* Use ALT floating point mode for ARB vertex programs, because they
79 * require 0^0 == 1.
80 */
81 if (intel->ctx.Shader.CurrentVertexProgram == NULL)
82 floating_point_mode = GEN6_VS_FLOATING_POINT_MODE_ALT;
83
84 BEGIN_BATCH(6);
85 OUT_BATCH(_3DSTATE_VS << 16 | (6 - 2));
86 OUT_BATCH(brw->vs.prog_offset);
87 OUT_BATCH(floating_point_mode |
88 ((ALIGN(brw->sampler.count, 4)/4) << GEN6_VS_SAMPLER_COUNT_SHIFT));
89
90 if (brw->vs.prog_data->total_scratch) {
91 OUT_RELOC(brw->vs.scratch_bo,
92 I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
93 ffs(brw->vs.prog_data->total_scratch) - 11);
94 } else {
95 OUT_BATCH(0);
96 }
97
98 OUT_BATCH((1 << GEN6_VS_DISPATCH_START_GRF_SHIFT) |
99 (brw->vs.prog_data->urb_read_length << GEN6_VS_URB_READ_LENGTH_SHIFT) |
100 (0 << GEN6_VS_URB_ENTRY_READ_OFFSET_SHIFT));
101
102 OUT_BATCH(((brw->max_vs_threads - 1) << GEN6_VS_MAX_THREADS_SHIFT) |
103 GEN6_VS_STATISTICS_ENABLE |
104 GEN6_VS_ENABLE);
105 ADVANCE_BATCH();
106 }
107
108 const struct brw_tracked_state gen7_vs_state = {
109 .dirty = {
110 .mesa = _NEW_TRANSFORM | _NEW_PROGRAM_CONSTANTS,
111 .brw = (BRW_NEW_CONTEXT |
112 BRW_NEW_VERTEX_PROGRAM |
113 BRW_NEW_VS_BINDING_TABLE |
114 BRW_NEW_BATCH),
115 .cache = CACHE_NEW_VS_PROG | CACHE_NEW_SAMPLER
116 },
117 .emit = upload_vs_state,
118 };