src/mesa/drivers/dri/i965/gen7_vs_state.c

   1 /*
   2  * Copyright © 2011 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include "brw_context.h"
  25 #include "brw_state.h"
  26 #include "brw_defines.h"
  27 #include "brw_util.h"
  28 #include "program/prog_parameter.h"
  29 #include "program/prog_statevars.h"
  30 #include "intel_batchbuffer.h"
  31
  32
  33 void
  34 gen7_upload_constant_state(struct brw_context *brw,
  35                            const struct brw_stage_state *stage_state,
  36                            bool active, unsigned opcode)
  37 {
  38    uint32_t mocs = brw->gen < 8 ? GEN7_MOCS_L3 : 0;
  39
  40    /* Disable if the shader stage is inactive or there are no push constants. */
  41    active = active && stage_state->push_const_size != 0;
  42
  43    int dwords = brw->gen >= 8 ? 11 : 7;
  44    BEGIN_BATCH(dwords);
  45    OUT_BATCH(opcode << 16 | (dwords - 2));
  46    OUT_BATCH(active ? stage_state->push_const_size : 0);
  47    OUT_BATCH(0);
  48    /* Pointer to the constant buffer.  Covered by the set of state flags
  49     * from gen6_prepare_wm_contants
  50     */
  51    OUT_BATCH(active ? (stage_state->push_const_offset | mocs) : 0);
  52    OUT_BATCH(0);
  53    OUT_BATCH(0);
  54    OUT_BATCH(0);
  55    if (brw->gen >= 8) {
  56       OUT_BATCH(0);
  57       OUT_BATCH(0);
  58       OUT_BATCH(0);
  59       OUT_BATCH(0);
  60    }
  61
  62    ADVANCE_BATCH();
  63 }
  64
  65
  66 static void
  67 upload_vs_state(struct brw_context *brw)
  68 {
  69    struct gl_context *ctx = &brw->ctx;
  70    const struct brw_stage_state *stage_state = &brw->vs.base;
  71    uint32_t floating_point_mode = 0;
  72    const int max_threads_shift = brw->is_haswell ?
  73       HSW_VS_MAX_THREADS_SHIFT : GEN6_VS_MAX_THREADS_SHIFT;
  74
  75    if (!brw->is_haswell)
  76       gen7_emit_vs_workaround_flush(brw);
  77
  78    gen7_upload_constant_state(brw, stage_state, true /* active */,
  79                               _3DSTATE_CONSTANT_VS);
  80
  81    /* Use ALT floating point mode for ARB vertex programs, because they
  82     * require 0^0 == 1.
  83     */
  84    if (ctx->_Shader->CurrentProgram[MESA_SHADER_VERTEX] == NULL)
  85       floating_point_mode = GEN6_VS_FLOATING_POINT_MODE_ALT;
  86
  87    BEGIN_BATCH(6);
  88    OUT_BATCH(_3DSTATE_VS << 16 | (6 - 2));
  89    OUT_BATCH(stage_state->prog_offset);
  90    OUT_BATCH(floating_point_mode |
  91              ((ALIGN(stage_state->sampler_count, 4)/4) <<
  92               GEN6_VS_SAMPLER_COUNT_SHIFT) |
  93              ((brw->vs.prog_data->base.base.binding_table.size_bytes / 4) <<
  94               GEN6_VS_BINDING_TABLE_ENTRY_COUNT_SHIFT));
  95
  96    if (brw->vs.prog_data->base.total_scratch) {
  97       OUT_RELOC(stage_state->scratch_bo,
  98                 I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
  99                 ffs(brw->vs.prog_data->base.total_scratch) - 11);
 100    } else {
 101       OUT_BATCH(0);
 102    }
 103
 104    OUT_BATCH((brw->vs.prog_data->base.dispatch_grf_start_reg <<
 105               GEN6_VS_DISPATCH_START_GRF_SHIFT) |
 106              (brw->vs.prog_data->base.urb_read_length << GEN6_VS_URB_READ_LENGTH_SHIFT) |
 107              (0 << GEN6_VS_URB_ENTRY_READ_OFFSET_SHIFT));
 108
 109    OUT_BATCH(((brw->max_vs_threads - 1) << max_threads_shift) |
 110              GEN6_VS_STATISTICS_ENABLE |
 111              GEN6_VS_ENABLE);
 112    ADVANCE_BATCH();
 113 }
 114
 115 const struct brw_tracked_state gen7_vs_state = {
 116    .dirty = {
 117       .mesa  = _NEW_TRANSFORM | _NEW_PROGRAM_CONSTANTS,
 118       .brw   = (BRW_NEW_CONTEXT |
 119                 BRW_NEW_VERTEX_PROGRAM |
 120                 BRW_NEW_BATCH |
 121                 BRW_NEW_PUSH_CONSTANT_ALLOCATION),
 122       .cache = CACHE_NEW_VS_PROG
 123    },
 124    .emit = upload_vs_state,
 125 };