src/mesa/drivers/dri/i965/gen7_vs_state.c

   1 /*
   2  * Copyright © 2011 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include "brw_context.h"
  25 #include "brw_state.h"
  26 #include "brw_defines.h"
  27 #include "brw_util.h"
  28 #include "program/prog_parameter.h"
  29 #include "program/prog_statevars.h"
  30 #include "intel_batchbuffer.h"
  31
  32
  33 void
  34 gen7_upload_constant_state(struct brw_context *brw,
  35                            const struct brw_stage_state *stage_state,
  36                            bool active, unsigned opcode)
  37 {
  38    uint32_t mocs = brw->gen < 8 ? GEN7_MOCS_L3 : 0;
  39
  40    /* Disable if the shader stage is inactive or there are no push constants. */
  41    active = active && stage_state->push_const_size != 0;
  42
  43    int dwords = brw->gen >= 8 ? 11 : 7;
  44    BEGIN_BATCH(dwords);
  45    OUT_BATCH(opcode << 16 | (dwords - 2));
  46
  47    /* Workaround for SKL+ (we use option #2 until we have a need for more
  48     * constant buffers). This comes from the documentation for 3DSTATE_CONSTANT_*
  49     *
  50     * The driver must ensure The following case does not occur without a flush
  51     * to the 3D engine: 3DSTATE_CONSTANT_* with buffer 3 read length equal to
  52     * zero committed followed by a 3DSTATE_CONSTANT_* with buffer 0 read length
  53     * not equal to zero committed. Possible ways to avoid this condition
  54     * include:
  55     *     1. always force buffer 3 to have a non zero read length
  56     *     2. always force buffer 0 to a zero read length
  57     */
  58    if (brw->gen >= 9 && active) {
  59       OUT_BATCH(0);
  60       OUT_BATCH(stage_state->push_const_size);
  61    } else {
  62       OUT_BATCH(active ? stage_state->push_const_size : 0);
  63       OUT_BATCH(0);
  64    }
  65
  66    /* Pointer to the constant buffer.  Covered by the set of state flags
  67     * from gen6_prepare_wm_contants
  68     */
  69    if (brw->gen >= 9 && active) {
  70       OUT_BATCH(0);
  71       OUT_BATCH(0);
  72       OUT_BATCH(0);
  73       OUT_BATCH(0);
  74       /* XXX: When using buffers other than 0, you need to specify the
  75        * graphics virtual address regardless of INSPM/debug bits
  76        */
  77       OUT_RELOC64(brw->batch.bo, I915_GEM_DOMAIN_RENDER, 0,
  78                   stage_state->push_const_offset);
  79       OUT_BATCH(0);
  80       OUT_BATCH(0);
  81    } else if (brw->gen>= 8) {
  82       OUT_BATCH(active ? (stage_state->push_const_offset | mocs) : 0);
  83       OUT_BATCH(0);
  84       OUT_BATCH(0);
  85       OUT_BATCH(0);
  86       OUT_BATCH(0);
  87       OUT_BATCH(0);
  88       OUT_BATCH(0);
  89       OUT_BATCH(0);
  90    } else {
  91       OUT_BATCH(active ? (stage_state->push_const_offset | mocs) : 0);
  92       OUT_BATCH(0);
  93       OUT_BATCH(0);
  94       OUT_BATCH(0);
  95    }
  96
  97    ADVANCE_BATCH();
  98
  99    /* On SKL+ the new constants don't take effect until the next corresponding
 100     * 3DSTATE_BINDING_TABLE_POINTER_* command is parsed so we need to ensure
 101     * that is sent
 102     */
 103    if (brw->gen >= 9)
 104       brw->ctx.NewDriverState |= BRW_NEW_SURFACES;
 105 }
 106
 107 static void
 108 upload_vs_state(struct brw_context *brw)
 109 {
 110    const struct brw_stage_state *stage_state = &brw->vs.base;
 111    uint32_t floating_point_mode = 0;
 112    const int max_threads_shift = brw->is_haswell ?
 113       HSW_VS_MAX_THREADS_SHIFT : GEN6_VS_MAX_THREADS_SHIFT;
 114    const struct brw_vue_prog_data *prog_data = &brw->vs.prog_data->base;
 115
 116    if (!brw->is_haswell && !brw->is_baytrail)
 117       gen7_emit_vs_workaround_flush(brw);
 118
 119    if (brw->vs.prog_data->base.base.use_alt_mode)
 120       floating_point_mode = GEN6_VS_FLOATING_POINT_MODE_ALT;
 121
 122    BEGIN_BATCH(6);
 123    OUT_BATCH(_3DSTATE_VS << 16 | (6 - 2));
 124    OUT_BATCH(stage_state->prog_offset);
 125    OUT_BATCH(floating_point_mode |
 126              ((ALIGN(stage_state->sampler_count, 4)/4) <<
 127               GEN6_VS_SAMPLER_COUNT_SHIFT) |
 128              ((brw->vs.prog_data->base.base.binding_table.size_bytes / 4) <<
 129               GEN6_VS_BINDING_TABLE_ENTRY_COUNT_SHIFT));
 130
 131    if (prog_data->base.total_scratch) {
 132       OUT_RELOC(stage_state->scratch_bo,
 133                 I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
 134                 ffs(prog_data->base.total_scratch) - 11);
 135    } else {
 136       OUT_BATCH(0);
 137    }
 138
 139    OUT_BATCH((prog_data->base.dispatch_grf_start_reg <<
 140               GEN6_VS_DISPATCH_START_GRF_SHIFT) |
 141              (prog_data->urb_read_length << GEN6_VS_URB_READ_LENGTH_SHIFT) |
 142              (0 << GEN6_VS_URB_ENTRY_READ_OFFSET_SHIFT));
 143
 144    OUT_BATCH(((brw->max_vs_threads - 1) << max_threads_shift) |
 145              GEN6_VS_STATISTICS_ENABLE |
 146              GEN6_VS_ENABLE);
 147    ADVANCE_BATCH();
 148 }
 149
 150 const struct brw_tracked_state gen7_vs_state = {
 151    .dirty = {
 152       .mesa  = _NEW_TRANSFORM,
 153       .brw   = BRW_NEW_BATCH |
 154                BRW_NEW_CONTEXT |
 155                BRW_NEW_VS_PROG_DATA,
 156    },
 157    .emit = upload_vs_state,
 158 };