src/mesa/drivers/dri/i965/gen7_vs_state.c

   1 /*
   2  * Copyright © 2011 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include "brw_context.h"
  25 #include "brw_state.h"
  26 #include "brw_defines.h"
  27 #include "brw_util.h"
  28 #include "program/prog_parameter.h"
  29 #include "program/prog_statevars.h"
  30 #include "intel_batchbuffer.h"
  31
  32 static void
  33 upload_vs_state(struct brw_context *brw)
  34 {
  35    struct gl_context *ctx = &brw->ctx;
  36    const struct brw_stage_state *stage_state = &brw->vs.base;
  37    uint32_t floating_point_mode = 0;
  38    const int max_threads_shift = brw->is_haswell ?
  39       HSW_VS_MAX_THREADS_SHIFT : GEN6_VS_MAX_THREADS_SHIFT;
  40
  41    gen7_emit_vs_workaround_flush(brw);
  42
  43    /* BRW_NEW_VS_BINDING_TABLE */
  44    BEGIN_BATCH(2);
  45    OUT_BATCH(_3DSTATE_BINDING_TABLE_POINTERS_VS << 16 | (2 - 2));
  46    OUT_BATCH(stage_state->bind_bo_offset);
  47    ADVANCE_BATCH();
  48
  49    /* CACHE_NEW_SAMPLER */
  50    BEGIN_BATCH(2);
  51    OUT_BATCH(_3DSTATE_SAMPLER_STATE_POINTERS_VS << 16 | (2 - 2));
  52    OUT_BATCH(stage_state->sampler_offset);
  53    ADVANCE_BATCH();
  54
  55    if (stage_state->push_const_size == 0) {
  56       /* Disable the push constant buffers. */
  57       BEGIN_BATCH(7);
  58       OUT_BATCH(_3DSTATE_CONSTANT_VS << 16 | (7 - 2));
  59       OUT_BATCH(0);
  60       OUT_BATCH(0);
  61       OUT_BATCH(0);
  62       OUT_BATCH(0);
  63       OUT_BATCH(0);
  64       OUT_BATCH(0);
  65       ADVANCE_BATCH();
  66    } else {
  67       BEGIN_BATCH(7);
  68       OUT_BATCH(_3DSTATE_CONSTANT_VS << 16 | (7 - 2));
  69       OUT_BATCH(stage_state->push_const_size);
  70       OUT_BATCH(0);
  71       /* Pointer to the VS constant buffer.  Covered by the set of
  72        * state flags from gen6_prepare_wm_contants
  73        */
  74       OUT_BATCH(stage_state->push_const_offset | GEN7_MOCS_L3);
  75       OUT_BATCH(0);
  76       OUT_BATCH(0);
  77       OUT_BATCH(0);
  78       ADVANCE_BATCH();
  79    }
  80
  81    /* Use ALT floating point mode for ARB vertex programs, because they
  82     * require 0^0 == 1.
  83     */
  84    if (ctx->Shader.CurrentVertexProgram == NULL)
  85       floating_point_mode = GEN6_VS_FLOATING_POINT_MODE_ALT;
  86
  87    BEGIN_BATCH(6);
  88    OUT_BATCH(_3DSTATE_VS << 16 | (6 - 2));
  89    OUT_BATCH(stage_state->prog_offset);
  90    OUT_BATCH(floating_point_mode |
  91              ((ALIGN(stage_state->sampler_count, 4)/4) <<
  92               GEN6_VS_SAMPLER_COUNT_SHIFT));
  93
  94    if (brw->vs.prog_data->base.total_scratch) {
  95       OUT_RELOC(stage_state->scratch_bo,
  96                 I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
  97                 ffs(brw->vs.prog_data->base.total_scratch) - 11);
  98    } else {
  99       OUT_BATCH(0);
 100    }
 101
 102    OUT_BATCH((brw->vs.prog_data->base.dispatch_grf_start_reg <<
 103               GEN6_VS_DISPATCH_START_GRF_SHIFT) |
 104              (brw->vs.prog_data->base.urb_read_length << GEN6_VS_URB_READ_LENGTH_SHIFT) |
 105              (0 << GEN6_VS_URB_ENTRY_READ_OFFSET_SHIFT));
 106
 107    OUT_BATCH(((brw->max_vs_threads - 1) << max_threads_shift) |
 108              GEN6_VS_STATISTICS_ENABLE |
 109              GEN6_VS_ENABLE);
 110    ADVANCE_BATCH();
 111 }
 112
 113 const struct brw_tracked_state gen7_vs_state = {
 114    .dirty = {
 115       .mesa  = _NEW_TRANSFORM | _NEW_PROGRAM_CONSTANTS,
 116       .brw   = (BRW_NEW_CONTEXT |
 117                 BRW_NEW_VERTEX_PROGRAM |
 118                 BRW_NEW_VS_BINDING_TABLE |
 119                 BRW_NEW_BATCH |
 120                 BRW_NEW_PUSH_CONSTANT_ALLOCATION),
 121       .cache = CACHE_NEW_VS_PROG | CACHE_NEW_SAMPLER
 122    },
 123    .emit = upload_vs_state,
 124 };