i965: Use 0 for the number of binding table entries in 3DSTATE_(VS|WM).
[mesa.git] / src / mesa / drivers / dri / i965 / gen7_vs_state.c
1 /*
2 * Copyright © 2011 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include "brw_context.h"
25 #include "brw_state.h"
26 #include "brw_defines.h"
27 #include "brw_util.h"
28 #include "program/prog_parameter.h"
29 #include "program/prog_statevars.h"
30 #include "intel_batchbuffer.h"
31
32 static void
33 upload_vs_state(struct brw_context *brw)
34 {
35 struct intel_context *intel = &brw->intel;
36 uint32_t floating_point_mode = 0;
37
38 BEGIN_BATCH(2);
39 OUT_BATCH(_3DSTATE_BINDING_TABLE_POINTERS_VS << 16 | (2 - 2));
40 OUT_BATCH(brw->vs.bind_bo_offset);
41 ADVANCE_BATCH();
42
43 if (brw->vs.push_const_size == 0) {
44 /* Disable the push constant buffers. */
45 BEGIN_BATCH(7);
46 OUT_BATCH(_3DSTATE_CONSTANT_VS << 16 | (7 - 2));
47 OUT_BATCH(0);
48 OUT_BATCH(0);
49 OUT_BATCH(0);
50 OUT_BATCH(0);
51 OUT_BATCH(0);
52 OUT_BATCH(0);
53 ADVANCE_BATCH();
54 } else {
55 BEGIN_BATCH(7);
56 OUT_BATCH(_3DSTATE_CONSTANT_VS << 16 | (7 - 2));
57 OUT_BATCH(brw->vs.push_const_size);
58 OUT_BATCH(0);
59 /* Pointer to the VS constant buffer. Covered by the set of
60 * state flags from gen6_prepare_wm_contants
61 */
62 OUT_BATCH(brw->vs.push_const_offset);
63 OUT_BATCH(0);
64 OUT_BATCH(0);
65 OUT_BATCH(0);
66 ADVANCE_BATCH();
67 }
68
69 /* Use ALT floating point mode for ARB vertex programs, because they
70 * require 0^0 == 1.
71 */
72 if (intel->ctx.Shader.CurrentVertexProgram == NULL)
73 floating_point_mode = GEN6_VS_FLOATING_POINT_MODE_ALT;
74
75 BEGIN_BATCH(6);
76 OUT_BATCH(_3DSTATE_VS << 16 | (6 - 2));
77 OUT_BATCH(brw->vs.prog_offset);
78 OUT_BATCH((0 << GEN6_VS_SAMPLER_COUNT_SHIFT) | floating_point_mode);
79
80 if (brw->vs.prog_data->total_scratch) {
81 OUT_RELOC(brw->vs.scratch_bo,
82 I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
83 ffs(brw->vs.prog_data->total_scratch) - 11);
84 } else {
85 OUT_BATCH(0);
86 }
87
88 OUT_BATCH((1 << GEN6_VS_DISPATCH_START_GRF_SHIFT) |
89 (brw->vs.prog_data->urb_read_length << GEN6_VS_URB_READ_LENGTH_SHIFT) |
90 (0 << GEN6_VS_URB_ENTRY_READ_OFFSET_SHIFT));
91
92 OUT_BATCH(((brw->max_vs_threads - 1) << GEN6_VS_MAX_THREADS_SHIFT) |
93 GEN6_VS_STATISTICS_ENABLE |
94 GEN6_VS_ENABLE);
95 ADVANCE_BATCH();
96 }
97
98 const struct brw_tracked_state gen7_vs_state = {
99 .dirty = {
100 .mesa = _NEW_TRANSFORM | _NEW_PROGRAM_CONSTANTS,
101 .brw = (BRW_NEW_CURBE_OFFSETS |
102 BRW_NEW_URB_FENCE |
103 BRW_NEW_CONTEXT |
104 BRW_NEW_VERTEX_PROGRAM |
105 BRW_NEW_VS_BINDING_TABLE |
106 BRW_NEW_BATCH),
107 .cache = CACHE_NEW_VS_PROG
108 },
109 .emit = upload_vs_state,
110 };