2 * Copyright © 2011 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 #include "brw_context.h"
26 #include "brw_state.h"
27 #include "brw_defines.h"
30 #include "program/program.h"
31 #include "program/prog_parameter.h"
32 #include "program/prog_statevars.h"
33 #include "main/framebuffer.h"
34 #include "intel_batchbuffer.h"
37 upload_wm_state(struct brw_context
*brw
)
39 struct gl_context
*ctx
= &brw
->ctx
;
40 /* BRW_NEW_FS_PROG_DATA */
41 const struct brw_wm_prog_data
*prog_data
=
42 brw_wm_prog_data(brw
->wm
.base
.prog_data
);
43 bool writes_depth
= prog_data
->computed_depth_mode
!= BRW_PSCDEPTH_OFF
;
47 const bool multisampled_fbo
= _mesa_geometric_samples(ctx
->DrawBuffer
) > 1;
50 dw1
|= GEN7_WM_STATISTICS_ENABLE
;
51 dw1
|= GEN7_WM_LINE_AA_WIDTH_1_0
;
52 dw1
|= GEN7_WM_LINE_END_CAP_AA_WIDTH_0_5
;
55 if (ctx
->Line
.StippleFlag
)
56 dw1
|= GEN7_WM_LINE_STIPPLE_ENABLE
;
59 if (ctx
->Polygon
.StippleFlag
)
60 dw1
|= GEN7_WM_POLYGON_STIPPLE_ENABLE
;
62 if (prog_data
->uses_src_depth
)
63 dw1
|= GEN7_WM_USES_SOURCE_DEPTH
;
65 if (prog_data
->uses_src_w
)
66 dw1
|= GEN7_WM_USES_SOURCE_W
;
68 dw1
|= prog_data
->computed_depth_mode
<< GEN7_WM_COMPUTED_DEPTH_MODE_SHIFT
;
69 dw1
|= prog_data
->barycentric_interp_modes
<<
70 GEN7_WM_BARYCENTRIC_INTERPOLATION_MODE_SHIFT
;
72 /* _NEW_COLOR, _NEW_MULTISAMPLE */
73 /* Enable if the pixel shader kernel generates and outputs oMask.
75 if (prog_data
->uses_kill
|| ctx
->Color
.AlphaEnabled
||
76 ctx
->Multisample
.SampleAlphaToCoverage
||
77 prog_data
->uses_omask
) {
78 dw1
|= GEN7_WM_KILL_ENABLE
;
81 /* _NEW_BUFFERS | _NEW_COLOR */
82 if (brw_color_buffer_write_enabled(brw
) || writes_depth
||
83 prog_data
->has_side_effects
|| dw1
& GEN7_WM_KILL_ENABLE
) {
84 dw1
|= GEN7_WM_DISPATCH_ENABLE
;
86 if (multisampled_fbo
) {
87 /* _NEW_MULTISAMPLE */
88 if (ctx
->Multisample
.Enabled
)
89 dw1
|= GEN7_WM_MSRAST_ON_PATTERN
;
91 dw1
|= GEN7_WM_MSRAST_OFF_PIXEL
;
93 if (prog_data
->persample_dispatch
)
94 dw2
|= GEN7_WM_MSDISPMODE_PERSAMPLE
;
96 dw2
|= GEN7_WM_MSDISPMODE_PERPIXEL
;
98 dw1
|= GEN7_WM_MSRAST_OFF_PIXEL
;
99 dw2
|= GEN7_WM_MSDISPMODE_PERSAMPLE
;
102 if (prog_data
->uses_sample_mask
) {
103 dw1
|= GEN7_WM_USES_INPUT_COVERAGE_MASK
;
106 /* BRW_NEW_FS_PROG_DATA */
107 if (prog_data
->early_fragment_tests
)
108 dw1
|= GEN7_WM_EARLY_DS_CONTROL_PREPS
;
109 else if (prog_data
->has_side_effects
)
110 dw1
|= GEN7_WM_EARLY_DS_CONTROL_PSEXEC
;
112 /* The "UAV access enable" bits are unnecessary on HSW because they only
113 * seem to have an effect on the HW-assisted coherency mechanism which we
114 * don't need, and the rasterization-related UAV_ONLY flag and the
115 * DISPATCH_ENABLE bit can be set independently from it.
116 * C.f. gen8_upload_ps_extra().
118 * BRW_NEW_FRAGMENT_PROGRAM | BRW_NEW_FS_PROG_DATA | _NEW_BUFFERS | _NEW_COLOR
120 if (brw
->is_haswell
&&
121 !(brw_color_buffer_write_enabled(brw
) || writes_depth
) &&
122 prog_data
->has_side_effects
)
123 dw2
|= HSW_WM_UAV_ONLY
;
126 OUT_BATCH(_3DSTATE_WM
<< 16 | (3 - 2));
132 const struct brw_tracked_state gen7_wm_state
= {
134 .mesa
= _NEW_BUFFERS
|
139 .brw
= BRW_NEW_BATCH
|
141 BRW_NEW_FS_PROG_DATA
,
143 .emit
= upload_wm_state
,
147 gen7_upload_ps_state(struct brw_context
*brw
,
148 const struct brw_stage_state
*stage_state
,
149 const struct brw_wm_prog_data
*prog_data
,
150 bool enable_dual_src_blend
, unsigned sample_mask
,
151 unsigned fast_clear_op
)
153 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
154 uint32_t dw2
, dw4
, dw5
, ksp0
, ksp2
;
155 const int max_threads_shift
= brw
->is_haswell
?
156 HSW_PS_MAX_THREADS_SHIFT
: IVB_PS_MAX_THREADS_SHIFT
;
158 dw2
= dw4
= dw5
= ksp2
= 0;
160 const unsigned sampler_count
=
161 DIV_ROUND_UP(CLAMP(stage_state
->sampler_count
, 0, 16), 4);
162 dw2
|= SET_FIELD(sampler_count
, GEN7_PS_SAMPLER_COUNT
);
164 dw2
|= ((prog_data
->base
.binding_table
.size_bytes
/ 4) <<
165 GEN7_PS_BINDING_TABLE_ENTRY_COUNT_SHIFT
);
167 if (prog_data
->base
.use_alt_mode
)
168 dw2
|= GEN7_PS_FLOATING_POINT_MODE_ALT
;
170 /* Haswell requires the sample mask to be set in this packet as well as
171 * in 3DSTATE_SAMPLE_MASK; the values should match. */
172 /* _NEW_BUFFERS, _NEW_MULTISAMPLE */
174 dw4
|= SET_FIELD(sample_mask
, HSW_PS_SAMPLE_MASK
);
176 dw4
|= (devinfo
->max_wm_threads
- 1) << max_threads_shift
;
178 if (prog_data
->base
.nr_params
> 0)
179 dw4
|= GEN7_PS_PUSH_CONSTANT_ENABLE
;
181 /* From the IVB PRM, volume 2 part 1, page 287:
182 * "This bit is inserted in the PS payload header and made available to
183 * the DataPort (either via the message header or via header bypass) to
184 * indicate that oMask data (one or two phases) is included in Render
185 * Target Write messages. If present, the oMask data is used to mask off
188 if (prog_data
->uses_omask
)
189 dw4
|= GEN7_PS_OMASK_TO_RENDER_TARGET
;
191 /* From the IVB PRM, volume 2 part 1, page 287:
192 * "If the PS kernel does not need the Position XY Offsets to
193 * compute a Position Value, then this field should be programmed
194 * to POSOFFSET_NONE."
195 * "SW Recommendation: If the PS kernel needs the Position Offsets
196 * to compute a Position XY value, this field should match Position
197 * ZW Interpolation Mode to ensure a consistent position.xyzw
199 * We only require XY sample offsets. So, this recommendation doesn't
200 * look useful at the moment. We might need this in future.
202 if (prog_data
->uses_pos_offset
)
203 dw4
|= GEN7_PS_POSOFFSET_SAMPLE
;
205 dw4
|= GEN7_PS_POSOFFSET_NONE
;
207 /* The hardware wedges if you have this bit set but don't turn on any dual
208 * source blend factors.
210 if (enable_dual_src_blend
)
211 dw4
|= GEN7_PS_DUAL_SOURCE_BLEND_ENABLE
;
213 /* BRW_NEW_FS_PROG_DATA */
214 if (prog_data
->num_varying_inputs
!= 0)
215 dw4
|= GEN7_PS_ATTRIBUTE_ENABLE
;
217 dw4
|= fast_clear_op
;
219 if (prog_data
->dispatch_16
)
220 dw4
|= GEN7_PS_16_DISPATCH_ENABLE
;
222 if (prog_data
->dispatch_8
)
223 dw4
|= GEN7_PS_8_DISPATCH_ENABLE
;
225 dw5
|= prog_data
->base
.dispatch_grf_start_reg
<<
226 GEN7_PS_DISPATCH_START_GRF_SHIFT_0
;
227 dw5
|= prog_data
->dispatch_grf_start_reg_2
<<
228 GEN7_PS_DISPATCH_START_GRF_SHIFT_2
;
230 ksp0
= stage_state
->prog_offset
;
231 ksp2
= stage_state
->prog_offset
+ prog_data
->prog_offset_2
;
234 OUT_BATCH(_3DSTATE_PS
<< 16 | (8 - 2));
237 if (prog_data
->base
.total_scratch
) {
238 OUT_RELOC(brw
->wm
.base
.scratch_bo
,
239 I915_GEM_DOMAIN_RENDER
, I915_GEM_DOMAIN_RENDER
,
240 ffs(stage_state
->per_thread_scratch
) - 11);
246 OUT_BATCH(0); /* kernel 1 pointer */
252 upload_ps_state(struct brw_context
*brw
)
254 /* BRW_NEW_FS_PROG_DATA */
255 const struct brw_wm_prog_data
*prog_data
=
256 brw_wm_prog_data(brw
->wm
.base
.prog_data
);
257 const struct gl_context
*ctx
= &brw
->ctx
;
258 /* BRW_NEW_FS_PROG_DATA | _NEW_COLOR */
259 const bool enable_dual_src_blend
= prog_data
->dual_src_blend
&&
260 (ctx
->Color
.BlendEnabled
& 1) &&
261 ctx
->Color
.Blend
[0]._UsesDualSrc
;
262 /* _NEW_BUFFERS, _NEW_MULTISAMPLE */
263 const unsigned sample_mask
=
264 brw
->is_haswell
? gen6_determine_sample_mask(brw
) : 0;
266 gen7_upload_ps_state(brw
, &brw
->wm
.base
, prog_data
,
267 enable_dual_src_blend
, sample_mask
,
268 brw
->wm
.fast_clear_op
);
271 const struct brw_tracked_state gen7_ps_state
= {
273 .mesa
= _NEW_BUFFERS
|
276 .brw
= BRW_NEW_BATCH
|
278 BRW_NEW_FS_PROG_DATA
,
280 .emit
= upload_ps_state
,