src/mesa/drivers/dri/i965/gen7_wm_state.c

   1 /*
   2  * Copyright © 2011 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include <stdbool.h>
  25 #include "brw_context.h"
  26 #include "brw_state.h"
  27 #include "brw_defines.h"
  28 #include "brw_util.h"
  29 #include "brw_wm.h"
  30 #include "program/program.h"
  31 #include "program/prog_parameter.h"
  32 #include "program/prog_statevars.h"
  33 #include "main/framebuffer.h"
  34 #include "intel_batchbuffer.h"
  35
  36 static void
  37 upload_wm_state(struct brw_context *brw)
  38 {
  39    struct gl_context *ctx = &brw->ctx;
  40    /* BRW_NEW_FS_PROG_DATA */
  41    const struct brw_wm_prog_data *prog_data = brw->wm.prog_data;
  42    bool writes_depth = prog_data->computed_depth_mode != BRW_PSCDEPTH_OFF;
  43    uint32_t dw1, dw2;
  44
  45    /* _NEW_BUFFERS */
  46    const bool multisampled_fbo = _mesa_geometric_samples(ctx->DrawBuffer) > 1;
  47
  48    dw1 = dw2 = 0;
  49    dw1 |= GEN7_WM_STATISTICS_ENABLE;
  50    dw1 |= GEN7_WM_LINE_AA_WIDTH_1_0;
  51    dw1 |= GEN7_WM_LINE_END_CAP_AA_WIDTH_0_5;
  52
  53    /* _NEW_LINE */
  54    if (ctx->Line.StippleFlag)
  55       dw1 |= GEN7_WM_LINE_STIPPLE_ENABLE;
  56
  57    /* _NEW_POLYGON */
  58    if (ctx->Polygon.StippleFlag)
  59       dw1 |= GEN7_WM_POLYGON_STIPPLE_ENABLE;
  60
  61    if (prog_data->uses_src_depth)
  62       dw1 |= GEN7_WM_USES_SOURCE_DEPTH;
  63
  64    if (prog_data->uses_src_w)
  65       dw1 |= GEN7_WM_USES_SOURCE_W;
  66
  67    dw1 |= prog_data->computed_depth_mode << GEN7_WM_COMPUTED_DEPTH_MODE_SHIFT;
  68    dw1 |= prog_data->barycentric_interp_modes <<
  69       GEN7_WM_BARYCENTRIC_INTERPOLATION_MODE_SHIFT;
  70
  71    /* _NEW_COLOR, _NEW_MULTISAMPLE */
  72    /* Enable if the pixel shader kernel generates and outputs oMask.
  73     */
  74    if (prog_data->uses_kill || ctx->Color.AlphaEnabled ||
  75        ctx->Multisample.SampleAlphaToCoverage ||
  76        prog_data->uses_omask) {
  77       dw1 |= GEN7_WM_KILL_ENABLE;
  78    }
  79
  80    /* _NEW_BUFFERS | _NEW_COLOR */
  81    const bool active_fs_has_side_effects =
  82       _mesa_active_fragment_shader_has_side_effects(&brw->ctx);
  83    if (brw_color_buffer_write_enabled(brw) || writes_depth ||
  84        active_fs_has_side_effects || dw1 & GEN7_WM_KILL_ENABLE) {
  85       dw1 |= GEN7_WM_DISPATCH_ENABLE;
  86    }
  87    if (multisampled_fbo) {
  88       /* _NEW_MULTISAMPLE */
  89       if (ctx->Multisample.Enabled)
  90          dw1 |= GEN7_WM_MSRAST_ON_PATTERN;
  91       else
  92          dw1 |= GEN7_WM_MSRAST_OFF_PIXEL;
  93
  94       if (_mesa_get_min_invocations_per_fragment(ctx, brw->fragment_program, false) > 1)
  95          dw2 |= GEN7_WM_MSDISPMODE_PERSAMPLE;
  96       else
  97          dw2 |= GEN7_WM_MSDISPMODE_PERPIXEL;
  98    } else {
  99       dw1 |= GEN7_WM_MSRAST_OFF_PIXEL;
 100       dw2 |= GEN7_WM_MSDISPMODE_PERSAMPLE;
 101    }
 102
 103    if (prog_data->uses_sample_mask) {
 104       dw1 |= GEN7_WM_USES_INPUT_COVERAGE_MASK;
 105    }
 106
 107    /* BRW_NEW_FS_PROG_DATA */
 108    if (prog_data->early_fragment_tests)
 109       dw1 |= GEN7_WM_EARLY_DS_CONTROL_PREPS;
 110    else if (active_fs_has_side_effects)
 111       dw1 |= GEN7_WM_EARLY_DS_CONTROL_PSEXEC;
 112
 113    /* The "UAV access enable" bits are unnecessary on HSW because they only
 114     * seem to have an effect on the HW-assisted coherency mechanism which we
 115     * don't need, and the rasterization-related UAV_ONLY flag and the
 116     * DISPATCH_ENABLE bit can be set independently from it.
 117     * C.f. gen8_upload_ps_extra().
 118     *
 119     * BRW_NEW_FRAGMENT_PROGRAM | BRW_NEW_FS_PROG_DATA | _NEW_BUFFERS | _NEW_COLOR
 120     */
 121    if (brw->is_haswell &&
 122        !(brw_color_buffer_write_enabled(brw) || writes_depth) &&
 123        active_fs_has_side_effects)
 124       dw2 |= HSW_WM_UAV_ONLY;
 125
 126    BEGIN_BATCH(3);
 127    OUT_BATCH(_3DSTATE_WM << 16 | (3 - 2));
 128    OUT_BATCH(dw1);
 129    OUT_BATCH(dw2);
 130    ADVANCE_BATCH();
 131 }
 132
 133 const struct brw_tracked_state gen7_wm_state = {
 134    .dirty = {
 135       .mesa  = _NEW_BUFFERS |
 136                _NEW_COLOR |
 137                _NEW_LINE |
 138                _NEW_MULTISAMPLE |
 139                _NEW_POLYGON,
 140       .brw   = BRW_NEW_BATCH |
 141                BRW_NEW_FS_PROG_DATA,
 142    },
 143    .emit = upload_wm_state,
 144 };
 145
 146 static void
 147 gen7_upload_ps_state(struct brw_context *brw,
 148                      const struct gl_fragment_program *fp,
 149                      const struct brw_stage_state *stage_state,
 150                      const struct brw_wm_prog_data *prog_data,
 151                      bool enable_dual_src_blend, unsigned sample_mask,
 152                      unsigned fast_clear_op)
 153 {
 154    struct gl_context *ctx = &brw->ctx;
 155    uint32_t dw2, dw4, dw5, ksp0, ksp2;
 156    const int max_threads_shift = brw->is_haswell ?
 157       HSW_PS_MAX_THREADS_SHIFT : IVB_PS_MAX_THREADS_SHIFT;
 158
 159    dw2 = dw4 = dw5 = ksp2 = 0;
 160
 161    const unsigned sampler_count =
 162       DIV_ROUND_UP(CLAMP(stage_state->sampler_count, 0, 16), 4);
 163    dw2 |= SET_FIELD(sampler_count, GEN7_PS_SAMPLER_COUNT);
 164
 165    dw2 |= ((prog_data->base.binding_table.size_bytes / 4) <<
 166            GEN7_PS_BINDING_TABLE_ENTRY_COUNT_SHIFT);
 167
 168    if (prog_data->base.use_alt_mode)
 169       dw2 |= GEN7_PS_FLOATING_POINT_MODE_ALT;
 170
 171    /* Haswell requires the sample mask to be set in this packet as well as
 172     * in 3DSTATE_SAMPLE_MASK; the values should match. */
 173    /* _NEW_BUFFERS, _NEW_MULTISAMPLE */
 174    if (brw->is_haswell)
 175       dw4 |= SET_FIELD(sample_mask, HSW_PS_SAMPLE_MASK);
 176
 177    dw4 |= (brw->max_wm_threads - 1) << max_threads_shift;
 178
 179    if (prog_data->base.nr_params > 0)
 180       dw4 |= GEN7_PS_PUSH_CONSTANT_ENABLE;
 181
 182    /* From the IVB PRM, volume 2 part 1, page 287:
 183     * "This bit is inserted in the PS payload header and made available to
 184     * the DataPort (either via the message header or via header bypass) to
 185     * indicate that oMask data (one or two phases) is included in Render
 186     * Target Write messages. If present, the oMask data is used to mask off
 187     * samples."
 188     */
 189    if (prog_data->uses_omask)
 190       dw4 |= GEN7_PS_OMASK_TO_RENDER_TARGET;
 191
 192    /* From the IVB PRM, volume 2 part 1, page 287:
 193     * "If the PS kernel does not need the Position XY Offsets to
 194     * compute a Position Value, then this field should be programmed
 195     * to POSOFFSET_NONE."
 196     * "SW Recommendation: If the PS kernel needs the Position Offsets
 197     * to compute a Position XY value, this field should match Position
 198     * ZW Interpolation Mode to ensure a consistent position.xyzw
 199     * computation."
 200     * We only require XY sample offsets. So, this recommendation doesn't
 201     * look useful at the moment. We might need this in future.
 202     */
 203    if (prog_data->uses_pos_offset)
 204       dw4 |= GEN7_PS_POSOFFSET_SAMPLE;
 205    else
 206       dw4 |= GEN7_PS_POSOFFSET_NONE;
 207
 208    /* The hardware wedges if you have this bit set but don't turn on any dual
 209     * source blend factors.
 210     */
 211    if (enable_dual_src_blend)
 212       dw4 |= GEN7_PS_DUAL_SOURCE_BLEND_ENABLE;
 213
 214    /* BRW_NEW_FS_PROG_DATA */
 215    if (prog_data->num_varying_inputs != 0)
 216       dw4 |= GEN7_PS_ATTRIBUTE_ENABLE;
 217
 218    /* In case of non 1x per sample shading, only one of SIMD8 and SIMD16
 219     * should be enabled. We do 'SIMD16 only' dispatch if a SIMD16 shader
 220     * is successfully compiled. In majority of the cases that bring us
 221     * better performance than 'SIMD8 only' dispatch.
 222     */
 223    int min_inv_per_frag =
 224       _mesa_get_min_invocations_per_fragment(ctx, fp, false);
 225    assert(min_inv_per_frag >= 1);
 226
 227    if (prog_data->prog_offset_16 || prog_data->no_8) {
 228       dw4 |= GEN7_PS_16_DISPATCH_ENABLE;
 229       if (!prog_data->no_8 && min_inv_per_frag == 1) {
 230          dw4 |= GEN7_PS_8_DISPATCH_ENABLE;
 231          dw5 |= (prog_data->base.dispatch_grf_start_reg <<
 232                  GEN7_PS_DISPATCH_START_GRF_SHIFT_0);
 233          dw5 |= (prog_data->dispatch_grf_start_reg_16 <<
 234                  GEN7_PS_DISPATCH_START_GRF_SHIFT_2);
 235          ksp0 = stage_state->prog_offset;
 236          ksp2 = stage_state->prog_offset + prog_data->prog_offset_16;
 237       } else {
 238          dw5 |= (prog_data->dispatch_grf_start_reg_16 <<
 239                  GEN7_PS_DISPATCH_START_GRF_SHIFT_0);
 240          ksp0 = stage_state->prog_offset + prog_data->prog_offset_16;
 241       }
 242    }
 243    else {
 244       dw4 |= GEN7_PS_8_DISPATCH_ENABLE;
 245       dw5 |= (prog_data->base.dispatch_grf_start_reg <<
 246               GEN7_PS_DISPATCH_START_GRF_SHIFT_0);
 247       ksp0 = stage_state->prog_offset;
 248    }
 249
 250    dw4 |= fast_clear_op;
 251
 252    BEGIN_BATCH(8);
 253    OUT_BATCH(_3DSTATE_PS << 16 | (8 - 2));
 254    OUT_BATCH(ksp0);
 255    OUT_BATCH(dw2);
 256    if (prog_data->base.total_scratch) {
 257       OUT_RELOC(brw->wm.base.scratch_bo,
 258                 I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
 259                 ffs(prog_data->base.total_scratch) - 11);
 260    } else {
 261       OUT_BATCH(0);
 262    }
 263    OUT_BATCH(dw4);
 264    OUT_BATCH(dw5);
 265    OUT_BATCH(0); /* kernel 1 pointer */
 266    OUT_BATCH(ksp2);
 267    ADVANCE_BATCH();
 268 }
 269
 270 static void
 271 upload_ps_state(struct brw_context *brw)
 272 {
 273    /* BRW_NEW_FS_PROG_DATA */
 274    const struct brw_wm_prog_data *prog_data = brw->wm.prog_data;
 275    const struct gl_context *ctx = &brw->ctx;
 276    /* BRW_NEW_FS_PROG_DATA | _NEW_COLOR */
 277    const bool enable_dual_src_blend = prog_data->dual_src_blend &&
 278                                       (ctx->Color.BlendEnabled & 1) &&
 279                                       ctx->Color.Blend[0]._UsesDualSrc;
 280    /* _NEW_BUFFERS, _NEW_MULTISAMPLE */
 281    const unsigned sample_mask =
 282       brw->is_haswell ? gen6_determine_sample_mask(brw) : 0;
 283
 284    gen7_upload_ps_state(brw, brw->fragment_program, &brw->wm.base, prog_data,
 285                         enable_dual_src_blend, sample_mask,
 286                         brw->wm.fast_clear_op);
 287 }
 288
 289 const struct brw_tracked_state gen7_ps_state = {
 290    .dirty = {
 291       .mesa  = _NEW_BUFFERS |
 292                _NEW_COLOR |
 293                _NEW_MULTISAMPLE,
 294       .brw   = BRW_NEW_BATCH |
 295                BRW_NEW_FRAGMENT_PROGRAM |
 296                BRW_NEW_FS_PROG_DATA,
 297    },
 298    .emit = upload_ps_state,
 299 };