src/mesa/drivers/dri/i965/gen7_wm_state.c

   1 /*
   2  * Copyright © 2011 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include <stdbool.h>
  25 #include "brw_context.h"
  26 #include "brw_state.h"
  27 #include "brw_defines.h"
  28 #include "brw_util.h"
  29 #include "brw_wm.h"
  30 #include "program/prog_parameter.h"
  31 #include "program/prog_statevars.h"
  32 #include "intel_batchbuffer.h"
  33
  34 static void
  35 upload_wm_state(struct brw_context *brw)
  36 {
  37    struct intel_context *intel = &brw->intel;
  38    struct gl_context *ctx = &intel->ctx;
  39    const struct brw_fragment_program *fp =
  40       brw_fragment_program_const(brw->fragment_program);
  41    bool writes_depth = false;
  42    bool multisampled = false;
  43    uint32_t dw1, dw2;
  44
  45    /* _NEW_BUFFERS */
  46    if (ctx->DrawBuffer->_ColorDrawBuffers[0])
  47       multisampled = ctx->DrawBuffer->_ColorDrawBuffers[0]->NumSamples > 0;
  48
  49    dw1 = dw2 = 0;
  50    dw1 |= GEN7_WM_STATISTICS_ENABLE;
  51    dw1 |= GEN7_WM_LINE_AA_WIDTH_1_0;
  52    dw1 |= GEN7_WM_LINE_END_CAP_AA_WIDTH_0_5;
  53
  54    /* _NEW_LINE */
  55    if (ctx->Line.StippleFlag)
  56       dw1 |= GEN7_WM_LINE_STIPPLE_ENABLE;
  57
  58    /* _NEW_POLYGON */
  59    if (ctx->Polygon.StippleFlag)
  60       dw1 |= GEN7_WM_POLYGON_STIPPLE_ENABLE;
  61
  62    /* BRW_NEW_FRAGMENT_PROGRAM */
  63    if (fp->program.Base.InputsRead & FRAG_BIT_WPOS)
  64       dw1 |= GEN7_WM_USES_SOURCE_DEPTH | GEN7_WM_USES_SOURCE_W;
  65    if (fp->program.Base.OutputsWritten & BITFIELD64_BIT(FRAG_RESULT_DEPTH)) {
  66       writes_depth = true;
  67       dw1 |= GEN7_WM_PSCDEPTH_ON;
  68    }
  69    /* CACHE_NEW_WM_PROG */
  70    dw1 |= brw->wm.prog_data->barycentric_interp_modes <<
  71       GEN7_WM_BARYCENTRIC_INTERPOLATION_MODE_SHIFT;
  72
  73    /* _NEW_COLOR */
  74    if (fp->program.UsesKill || ctx->Color.AlphaEnabled)
  75       dw1 |= GEN7_WM_KILL_ENABLE;
  76
  77    /* _NEW_BUFFERS */
  78    if (brw_color_buffer_write_enabled(brw) || writes_depth ||
  79        dw1 & GEN7_WM_KILL_ENABLE) {
  80       dw1 |= GEN7_WM_DISPATCH_ENABLE;
  81    }
  82    if (multisampled) {
  83       dw1 |= GEN7_WM_MSRAST_ON_PATTERN;
  84       dw2 |= GEN7_WM_MSDISPMODE_PERPIXEL;
  85    } else {
  86       dw1 |= GEN7_WM_MSRAST_OFF_PIXEL;
  87       dw2 |= GEN7_WM_MSDISPMODE_PERSAMPLE;
  88    }
  89
  90    BEGIN_BATCH(3);
  91    OUT_BATCH(_3DSTATE_WM << 16 | (3 - 2));
  92    OUT_BATCH(dw1);
  93    OUT_BATCH(dw2);
  94    ADVANCE_BATCH();
  95 }
  96
  97 const struct brw_tracked_state gen7_wm_state = {
  98    .dirty = {
  99       .mesa  = (_NEW_LINE | _NEW_POLYGON |
 100                 _NEW_COLOR | _NEW_BUFFERS),
 101       .brw   = (BRW_NEW_FRAGMENT_PROGRAM |
 102                 BRW_NEW_BATCH),
 103       .cache = CACHE_NEW_WM_PROG,
 104    },
 105    .emit = upload_wm_state,
 106 };
 107
 108 static void
 109 upload_ps_state(struct brw_context *brw)
 110 {
 111    struct intel_context *intel = &brw->intel;
 112    uint32_t dw2, dw4, dw5;
 113    const int max_threads_shift = brw->intel.is_haswell ?
 114       HSW_PS_MAX_THREADS_SHIFT : IVB_PS_MAX_THREADS_SHIFT;
 115
 116    /* BRW_NEW_PS_BINDING_TABLE */
 117    BEGIN_BATCH(2);
 118    OUT_BATCH(_3DSTATE_BINDING_TABLE_POINTERS_PS << 16 | (2 - 2));
 119    OUT_BATCH(brw->wm.bind_bo_offset);
 120    ADVANCE_BATCH();
 121
 122    /* CACHE_NEW_SAMPLER */
 123    BEGIN_BATCH(2);
 124    OUT_BATCH(_3DSTATE_SAMPLER_STATE_POINTERS_PS << 16 | (2 - 2));
 125    OUT_BATCH(brw->sampler.offset);
 126    ADVANCE_BATCH();
 127
 128    /* CACHE_NEW_WM_PROG */
 129    if (brw->wm.prog_data->nr_params == 0) {
 130       /* Disable the push constant buffers. */
 131       BEGIN_BATCH(7);
 132       OUT_BATCH(_3DSTATE_CONSTANT_PS << 16 | (7 - 2));
 133       OUT_BATCH(0);
 134       OUT_BATCH(0);
 135       OUT_BATCH(0);
 136       OUT_BATCH(0);
 137       OUT_BATCH(0);
 138       OUT_BATCH(0);
 139       ADVANCE_BATCH();
 140    } else {
 141       BEGIN_BATCH(7);
 142       OUT_BATCH(_3DSTATE_CONSTANT_PS << 16 | (7 - 2));
 143
 144       OUT_BATCH(ALIGN(brw->wm.prog_data->nr_params,
 145                       brw->wm.prog_data->dispatch_width) / 8);
 146       OUT_BATCH(0);
 147       /* Pointer to the WM constant buffer.  Covered by the set of
 148        * state flags from gen6_upload_wm_push_constants.
 149        */
 150       OUT_BATCH(brw->wm.push_const_offset);
 151       OUT_BATCH(0);
 152       OUT_BATCH(0);
 153       OUT_BATCH(0);
 154       ADVANCE_BATCH();
 155    }
 156
 157    dw2 = dw4 = dw5 = 0;
 158
 159    /* CACHE_NEW_SAMPLER */
 160    dw2 |= (ALIGN(brw->sampler.count, 4) / 4) << GEN7_PS_SAMPLER_COUNT_SHIFT;
 161
 162    /* Use ALT floating point mode for ARB fragment programs, because they
 163     * require 0^0 == 1.  Even though _CurrentFragmentProgram is used for
 164     * rendering, CurrentFragmentProgram is used for this check to
 165     * differentiate between the GLSL and non-GLSL cases.
 166     */
 167    if (intel->ctx.Shader.CurrentFragmentProgram == NULL)
 168       dw2 |= GEN7_PS_FLOATING_POINT_MODE_ALT;
 169
 170    if (intel->is_haswell)
 171       dw4 |= SET_FIELD(1, HSW_PS_SAMPLE_MASK); /* 1 sample for now */
 172
 173    dw4 |= (brw->max_wm_threads - 1) << max_threads_shift;
 174
 175    /* CACHE_NEW_WM_PROG */
 176    if (brw->wm.prog_data->nr_params > 0)
 177       dw4 |= GEN7_PS_PUSH_CONSTANT_ENABLE;
 178
 179    /* BRW_NEW_FRAGMENT_PROGRAM */
 180    if (brw->fragment_program->Base.InputsRead != 0)
 181       dw4 |= GEN7_PS_ATTRIBUTE_ENABLE;
 182
 183    if (brw->wm.prog_data->dispatch_width == 8) {
 184       dw4 |= GEN7_PS_8_DISPATCH_ENABLE;
 185       if (brw->wm.prog_data->prog_offset_16)
 186          dw4 |= GEN7_PS_16_DISPATCH_ENABLE;
 187    } else {
 188       dw4 |= GEN7_PS_16_DISPATCH_ENABLE;
 189    }
 190
 191    dw5 |= (brw->wm.prog_data->first_curbe_grf <<
 192            GEN7_PS_DISPATCH_START_GRF_SHIFT_0);
 193    dw5 |= (brw->wm.prog_data->first_curbe_grf_16 <<
 194            GEN7_PS_DISPATCH_START_GRF_SHIFT_2);
 195
 196    BEGIN_BATCH(8);
 197    OUT_BATCH(_3DSTATE_PS << 16 | (8 - 2));
 198    OUT_BATCH(brw->wm.prog_offset);
 199    OUT_BATCH(dw2);
 200    if (brw->wm.prog_data->total_scratch) {
 201       OUT_RELOC(brw->wm.scratch_bo,
 202                 I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
 203                 ffs(brw->wm.prog_data->total_scratch) - 11);
 204    } else {
 205       OUT_BATCH(0);
 206    }
 207    OUT_BATCH(dw4);
 208    OUT_BATCH(dw5);
 209    OUT_BATCH(0); /* kernel 1 pointer */
 210    OUT_BATCH(brw->wm.prog_offset + brw->wm.prog_data->prog_offset_16);
 211    ADVANCE_BATCH();
 212 }
 213
 214 const struct brw_tracked_state gen7_ps_state = {
 215    .dirty = {
 216       .mesa  = _NEW_PROGRAM_CONSTANTS,
 217       .brw   = (BRW_NEW_FRAGMENT_PROGRAM |
 218                 BRW_NEW_PS_BINDING_TABLE |
 219                 BRW_NEW_BATCH),
 220       .cache = (CACHE_NEW_SAMPLER |
 221                 CACHE_NEW_WM_PROG)
 222    },
 223    .emit = upload_ps_state,
 224 };