2 * Copyright © 2011 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 #include "brw_context.h"
26 #include "brw_state.h"
27 #include "brw_defines.h"
30 #include "program/program.h"
31 #include "program/prog_parameter.h"
32 #include "program/prog_statevars.h"
33 #include "intel_batchbuffer.h"
36 upload_wm_state(struct brw_context
*brw
)
38 struct gl_context
*ctx
= &brw
->ctx
;
39 /* BRW_NEW_FRAGMENT_PROGRAM */
40 const struct brw_fragment_program
*fp
=
41 brw_fragment_program_const(brw
->fragment_program
);
42 /* BRW_NEW_FS_PROG_DATA */
43 const struct brw_wm_prog_data
*prog_data
= brw
->wm
.prog_data
;
44 bool writes_depth
= false;
48 bool multisampled_fbo
= ctx
->DrawBuffer
->Visual
.samples
> 1;
51 dw1
|= GEN7_WM_STATISTICS_ENABLE
;
52 dw1
|= GEN7_WM_LINE_AA_WIDTH_1_0
;
53 dw1
|= GEN7_WM_LINE_END_CAP_AA_WIDTH_0_5
;
56 if (ctx
->Line
.StippleFlag
)
57 dw1
|= GEN7_WM_LINE_STIPPLE_ENABLE
;
60 if (ctx
->Polygon
.StippleFlag
)
61 dw1
|= GEN7_WM_POLYGON_STIPPLE_ENABLE
;
63 if (fp
->program
.Base
.InputsRead
& VARYING_BIT_POS
)
64 dw1
|= GEN7_WM_USES_SOURCE_DEPTH
| GEN7_WM_USES_SOURCE_W
;
65 if (fp
->program
.Base
.OutputsWritten
& BITFIELD64_BIT(FRAG_RESULT_DEPTH
)) {
66 writes_depth
= fp
->program
.FragDepthLayout
!= FRAG_DEPTH_LAYOUT_UNCHANGED
;
68 switch (fp
->program
.FragDepthLayout
) {
69 case FRAG_DEPTH_LAYOUT_NONE
:
70 case FRAG_DEPTH_LAYOUT_ANY
:
71 dw1
|= GEN7_WM_PSCDEPTH_ON
;
73 case FRAG_DEPTH_LAYOUT_GREATER
:
74 dw1
|= GEN7_WM_PSCDEPTH_ON_GE
;
76 case FRAG_DEPTH_LAYOUT_LESS
:
77 dw1
|= GEN7_WM_PSCDEPTH_ON_LE
;
79 case FRAG_DEPTH_LAYOUT_UNCHANGED
:
83 dw1
|= prog_data
->barycentric_interp_modes
<<
84 GEN7_WM_BARYCENTRIC_INTERPOLATION_MODE_SHIFT
;
86 /* _NEW_COLOR, _NEW_MULTISAMPLE */
87 /* Enable if the pixel shader kernel generates and outputs oMask.
89 if (prog_data
->uses_kill
|| ctx
->Color
.AlphaEnabled
||
90 ctx
->Multisample
.SampleAlphaToCoverage
||
91 prog_data
->uses_omask
) {
92 dw1
|= GEN7_WM_KILL_ENABLE
;
95 /* _NEW_BUFFERS | _NEW_COLOR */
96 if (brw_color_buffer_write_enabled(brw
) || writes_depth
||
97 dw1
& GEN7_WM_KILL_ENABLE
) {
98 dw1
|= GEN7_WM_DISPATCH_ENABLE
;
100 if (multisampled_fbo
) {
101 /* _NEW_MULTISAMPLE */
102 if (ctx
->Multisample
.Enabled
)
103 dw1
|= GEN7_WM_MSRAST_ON_PATTERN
;
105 dw1
|= GEN7_WM_MSRAST_OFF_PIXEL
;
107 if (_mesa_get_min_invocations_per_fragment(ctx
, brw
->fragment_program
, false) > 1)
108 dw2
|= GEN7_WM_MSDISPMODE_PERSAMPLE
;
110 dw2
|= GEN7_WM_MSDISPMODE_PERPIXEL
;
112 dw1
|= GEN7_WM_MSRAST_OFF_PIXEL
;
113 dw2
|= GEN7_WM_MSDISPMODE_PERSAMPLE
;
116 if (fp
->program
.Base
.SystemValuesRead
& SYSTEM_BIT_SAMPLE_MASK_IN
) {
117 dw1
|= GEN7_WM_USES_INPUT_COVERAGE_MASK
;
121 OUT_BATCH(_3DSTATE_WM
<< 16 | (3 - 2));
127 const struct brw_tracked_state gen7_wm_state
= {
129 .mesa
= _NEW_BUFFERS
|
134 .brw
= BRW_NEW_BATCH
|
135 BRW_NEW_FRAGMENT_PROGRAM
|
136 BRW_NEW_FS_PROG_DATA
,
138 .emit
= upload_wm_state
,
142 upload_ps_state(struct brw_context
*brw
)
144 struct gl_context
*ctx
= &brw
->ctx
;
145 uint32_t dw2
, dw4
, dw5
, ksp0
, ksp2
;
146 const int max_threads_shift
= brw
->is_haswell
?
147 HSW_PS_MAX_THREADS_SHIFT
: IVB_PS_MAX_THREADS_SHIFT
;
149 /* BRW_NEW_FS_PROG_DATA */
150 const struct brw_wm_prog_data
*prog_data
= brw
->wm
.prog_data
;
152 dw2
= dw4
= dw5
= ksp2
= 0;
155 (ALIGN(brw
->wm
.base
.sampler_count
, 4) / 4) << GEN7_PS_SAMPLER_COUNT_SHIFT
;
157 dw2
|= ((prog_data
->base
.binding_table
.size_bytes
/ 4) <<
158 GEN7_PS_BINDING_TABLE_ENTRY_COUNT_SHIFT
);
160 /* Use ALT floating point mode for ARB fragment programs, because they
161 * require 0^0 == 1. Even though _CurrentFragmentProgram is used for
162 * rendering, CurrentProgram[MESA_SHADER_FRAGMENT] is used for this check
163 * to differentiate between the GLSL and non-GLSL cases.
165 /* BRW_NEW_FRAGMENT_PROGRAM */
166 if (ctx
->_Shader
->CurrentProgram
[MESA_SHADER_FRAGMENT
] == NULL
)
167 dw2
|= GEN7_PS_FLOATING_POINT_MODE_ALT
;
169 /* Haswell requires the sample mask to be set in this packet as well as
170 * in 3DSTATE_SAMPLE_MASK; the values should match. */
171 /* _NEW_BUFFERS, _NEW_MULTISAMPLE */
173 dw4
|= SET_FIELD(gen6_determine_sample_mask(brw
), HSW_PS_SAMPLE_MASK
);
175 dw4
|= (brw
->max_wm_threads
- 1) << max_threads_shift
;
177 if (prog_data
->base
.nr_params
> 0)
178 dw4
|= GEN7_PS_PUSH_CONSTANT_ENABLE
;
180 /* From the IVB PRM, volume 2 part 1, page 287:
181 * "This bit is inserted in the PS payload header and made available to
182 * the DataPort (either via the message header or via header bypass) to
183 * indicate that oMask data (one or two phases) is included in Render
184 * Target Write messages. If present, the oMask data is used to mask off
187 if (prog_data
->uses_omask
)
188 dw4
|= GEN7_PS_OMASK_TO_RENDER_TARGET
;
190 /* From the IVB PRM, volume 2 part 1, page 287:
191 * "If the PS kernel does not need the Position XY Offsets to
192 * compute a Position Value, then this field should be programmed
193 * to POSOFFSET_NONE."
194 * "SW Recommendation: If the PS kernel needs the Position Offsets
195 * to compute a Position XY value, this field should match Position
196 * ZW Interpolation Mode to ensure a consistent position.xyzw
198 * We only require XY sample offsets. So, this recommendation doesn't
199 * look useful at the moment. We might need this in future.
201 if (prog_data
->uses_pos_offset
)
202 dw4
|= GEN7_PS_POSOFFSET_SAMPLE
;
204 dw4
|= GEN7_PS_POSOFFSET_NONE
;
206 /* BRW_NEW_FS_PROG_DATA | _NEW_COLOR
208 * The hardware wedges if you have this bit set but don't turn on any dual
209 * source blend factors.
211 if (prog_data
->dual_src_blend
&&
212 (ctx
->Color
.BlendEnabled
& 1) &&
213 ctx
->Color
.Blend
[0]._UsesDualSrc
) {
214 dw4
|= GEN7_PS_DUAL_SOURCE_BLEND_ENABLE
;
217 /* BRW_NEW_FS_PROG_DATA */
218 if (prog_data
->num_varying_inputs
!= 0)
219 dw4
|= GEN7_PS_ATTRIBUTE_ENABLE
;
221 /* In case of non 1x per sample shading, only one of SIMD8 and SIMD16
222 * should be enabled. We do 'SIMD16 only' dispatch if a SIMD16 shader
223 * is successfully compiled. In majority of the cases that bring us
224 * better performance than 'SIMD8 only' dispatch.
226 int min_inv_per_frag
=
227 _mesa_get_min_invocations_per_fragment(ctx
, brw
->fragment_program
, false);
228 assert(min_inv_per_frag
>= 1);
230 if (prog_data
->prog_offset_16
|| prog_data
->no_8
) {
231 dw4
|= GEN7_PS_16_DISPATCH_ENABLE
;
232 if (!prog_data
->no_8
&& min_inv_per_frag
== 1) {
233 dw4
|= GEN7_PS_8_DISPATCH_ENABLE
;
234 dw5
|= (prog_data
->base
.dispatch_grf_start_reg
<<
235 GEN7_PS_DISPATCH_START_GRF_SHIFT_0
);
236 dw5
|= (prog_data
->dispatch_grf_start_reg_16
<<
237 GEN7_PS_DISPATCH_START_GRF_SHIFT_2
);
238 ksp0
= brw
->wm
.base
.prog_offset
;
239 ksp2
= brw
->wm
.base
.prog_offset
+ prog_data
->prog_offset_16
;
241 dw5
|= (prog_data
->dispatch_grf_start_reg_16
<<
242 GEN7_PS_DISPATCH_START_GRF_SHIFT_0
);
243 ksp0
= brw
->wm
.base
.prog_offset
+ prog_data
->prog_offset_16
;
247 dw4
|= GEN7_PS_8_DISPATCH_ENABLE
;
248 dw5
|= (prog_data
->base
.dispatch_grf_start_reg
<<
249 GEN7_PS_DISPATCH_START_GRF_SHIFT_0
);
250 ksp0
= brw
->wm
.base
.prog_offset
;
253 dw4
|= brw
->wm
.fast_clear_op
;
256 OUT_BATCH(_3DSTATE_PS
<< 16 | (8 - 2));
259 if (prog_data
->base
.total_scratch
) {
260 OUT_RELOC(brw
->wm
.base
.scratch_bo
,
261 I915_GEM_DOMAIN_RENDER
, I915_GEM_DOMAIN_RENDER
,
262 ffs(prog_data
->base
.total_scratch
) - 11);
268 OUT_BATCH(0); /* kernel 1 pointer */
273 const struct brw_tracked_state gen7_ps_state
= {
275 .mesa
= _NEW_BUFFERS
|
278 .brw
= BRW_NEW_BATCH
|
279 BRW_NEW_FRAGMENT_PROGRAM
|
280 BRW_NEW_FS_PROG_DATA
,
282 .emit
= upload_ps_state
,