src/mesa/drivers/dri/i965/gen7_wm_state.c

   1 /*
   2  * Copyright © 2011 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include <stdbool.h>
  25 #include "brw_context.h"
  26 #include "brw_state.h"
  27 #include "brw_defines.h"
  28 #include "brw_util.h"
  29 #include "brw_wm.h"
  30 #include "program/prog_parameter.h"
  31 #include "program/prog_statevars.h"
  32 #include "intel_batchbuffer.h"
  33
  34 static void
  35 upload_wm_state(struct brw_context *brw)
  36 {
  37    struct intel_context *intel = &brw->intel;
  38    struct gl_context *ctx = &intel->ctx;
  39    const struct brw_fragment_program *fp =
  40       brw_fragment_program_const(brw->fragment_program);
  41    bool writes_depth = false;
  42    uint32_t dw1;
  43
  44    dw1 = 0;
  45    dw1 |= GEN7_WM_STATISTICS_ENABLE;
  46    dw1 |= GEN7_WM_LINE_AA_WIDTH_1_0;
  47    dw1 |= GEN7_WM_LINE_END_CAP_AA_WIDTH_0_5;
  48
  49    /* _NEW_LINE */
  50    if (ctx->Line.StippleFlag)
  51       dw1 |= GEN7_WM_LINE_STIPPLE_ENABLE;
  52
  53    /* _NEW_POLYGON */
  54    if (ctx->Polygon.StippleFlag)
  55       dw1 |= GEN7_WM_POLYGON_STIPPLE_ENABLE;
  56
  57    /* BRW_NEW_FRAGMENT_PROGRAM */
  58    if (fp->program.Base.InputsRead & FRAG_BIT_WPOS)
  59       dw1 |= GEN7_WM_USES_SOURCE_DEPTH | GEN7_WM_USES_SOURCE_W;
  60    if (fp->program.Base.OutputsWritten & BITFIELD64_BIT(FRAG_RESULT_DEPTH)) {
  61       writes_depth = true;
  62       dw1 |= GEN7_WM_PSCDEPTH_ON;
  63    }
  64    /* CACHE_NEW_WM_PROG */
  65    dw1 |= brw->wm.prog_data->barycentric_interp_modes <<
  66       GEN7_WM_BARYCENTRIC_INTERPOLATION_MODE_SHIFT;
  67
  68    /* _NEW_COLOR */
  69    if (fp->program.UsesKill || ctx->Color.AlphaEnabled)
  70       dw1 |= GEN7_WM_KILL_ENABLE;
  71
  72    /* _NEW_BUFFERS */
  73    if (brw_color_buffer_write_enabled(brw) || writes_depth ||
  74        dw1 & GEN7_WM_KILL_ENABLE) {
  75       dw1 |= GEN7_WM_DISPATCH_ENABLE;
  76    }
  77
  78    BEGIN_BATCH(3);
  79    OUT_BATCH(_3DSTATE_WM << 16 | (3 - 2));
  80    OUT_BATCH(dw1);
  81    OUT_BATCH(0);
  82    ADVANCE_BATCH();
  83 }
  84
  85 const struct brw_tracked_state gen7_wm_state = {
  86    .dirty = {
  87       .mesa  = (_NEW_LINE | _NEW_POLYGON |
  88                 _NEW_COLOR | _NEW_BUFFERS),
  89       .brw   = (BRW_NEW_FRAGMENT_PROGRAM |
  90                 BRW_NEW_BATCH),
  91       .cache = CACHE_NEW_WM_PROG,
  92    },
  93    .emit = upload_wm_state,
  94 };
  95
  96 static void
  97 upload_ps_state(struct brw_context *brw)
  98 {
  99    struct intel_context *intel = &brw->intel;
 100    uint32_t dw2, dw4, dw5;
 101
 102    /* BRW_NEW_PS_BINDING_TABLE */
 103    BEGIN_BATCH(2);
 104    OUT_BATCH(_3DSTATE_BINDING_TABLE_POINTERS_PS << 16 | (2 - 2));
 105    OUT_BATCH(brw->bind.bo_offset);
 106    ADVANCE_BATCH();
 107
 108    /* CACHE_NEW_SAMPLER */
 109    BEGIN_BATCH(2);
 110    OUT_BATCH(_3DSTATE_SAMPLER_STATE_POINTERS_PS << 16 | (2 - 2));
 111    OUT_BATCH(brw->sampler.offset);
 112    ADVANCE_BATCH();
 113
 114    /* CACHE_NEW_WM_PROG */
 115    if (brw->wm.prog_data->nr_params == 0) {
 116       /* Disable the push constant buffers. */
 117       BEGIN_BATCH(7);
 118       OUT_BATCH(_3DSTATE_CONSTANT_PS << 16 | (7 - 2));
 119       OUT_BATCH(0);
 120       OUT_BATCH(0);
 121       OUT_BATCH(0);
 122       OUT_BATCH(0);
 123       OUT_BATCH(0);
 124       OUT_BATCH(0);
 125       ADVANCE_BATCH();
 126    } else {
 127       BEGIN_BATCH(7);
 128       OUT_BATCH(_3DSTATE_CONSTANT_PS << 16 | (7 - 2));
 129
 130       OUT_BATCH(ALIGN(brw->wm.prog_data->nr_params,
 131                       brw->wm.prog_data->dispatch_width) / 8);
 132       OUT_BATCH(0);
 133       /* Pointer to the WM constant buffer.  Covered by the set of
 134        * state flags from gen6_upload_wm_push_constants.
 135        */
 136       OUT_BATCH(brw->wm.push_const_offset);
 137       OUT_BATCH(0);
 138       OUT_BATCH(0);
 139       OUT_BATCH(0);
 140       ADVANCE_BATCH();
 141    }
 142
 143    dw2 = dw4 = dw5 = 0;
 144
 145    /* CACHE_NEW_SAMPLER */
 146    dw2 |= (ALIGN(brw->sampler.count, 4) / 4) << GEN7_PS_SAMPLER_COUNT_SHIFT;
 147
 148    /* Use ALT floating point mode for ARB fragment programs, because they
 149     * require 0^0 == 1.  Even though _CurrentFragmentProgram is used for
 150     * rendering, CurrentFragmentProgram is used for this check to
 151     * differentiate between the GLSL and non-GLSL cases.
 152     */
 153    if (intel->ctx.Shader.CurrentFragmentProgram == NULL)
 154       dw2 |= GEN7_PS_FLOATING_POINT_MODE_ALT;
 155
 156    dw4 |= (brw->max_wm_threads - 1) << GEN7_PS_MAX_THREADS_SHIFT;
 157
 158    /* CACHE_NEW_WM_PROG */
 159    if (brw->wm.prog_data->nr_params > 0)
 160       dw4 |= GEN7_PS_PUSH_CONSTANT_ENABLE;
 161
 162    /* BRW_NEW_FRAGMENT_PROGRAM */
 163    if (brw->fragment_program->Base.InputsRead != 0)
 164       dw4 |= GEN7_PS_ATTRIBUTE_ENABLE;
 165
 166    if (brw->wm.prog_data->dispatch_width == 8) {
 167       dw4 |= GEN7_PS_8_DISPATCH_ENABLE;
 168       if (brw->wm.prog_data->prog_offset_16)
 169          dw4 |= GEN7_PS_16_DISPATCH_ENABLE;
 170    } else {
 171       dw4 |= GEN7_PS_16_DISPATCH_ENABLE;
 172    }
 173
 174    dw5 |= (brw->wm.prog_data->first_curbe_grf <<
 175            GEN7_PS_DISPATCH_START_GRF_SHIFT_0);
 176    dw5 |= (brw->wm.prog_data->first_curbe_grf_16 <<
 177            GEN7_PS_DISPATCH_START_GRF_SHIFT_2);
 178
 179    BEGIN_BATCH(8);
 180    OUT_BATCH(_3DSTATE_PS << 16 | (8 - 2));
 181    OUT_BATCH(brw->wm.prog_offset);
 182    OUT_BATCH(dw2);
 183    if (brw->wm.prog_data->total_scratch) {
 184       OUT_RELOC(brw->wm.scratch_bo,
 185                 I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
 186                 ffs(brw->wm.prog_data->total_scratch) - 11);
 187    } else {
 188       OUT_BATCH(0);
 189    }
 190    OUT_BATCH(dw4);
 191    OUT_BATCH(dw5);
 192    OUT_BATCH(0); /* kernel 1 pointer */
 193    OUT_BATCH(brw->wm.prog_offset + brw->wm.prog_data->prog_offset_16);
 194    ADVANCE_BATCH();
 195 }
 196
 197 const struct brw_tracked_state gen7_ps_state = {
 198    .dirty = {
 199       .mesa  = _NEW_PROGRAM_CONSTANTS,
 200       .brw   = (BRW_NEW_FRAGMENT_PROGRAM |
 201                 BRW_NEW_PS_BINDING_TABLE |
 202                 BRW_NEW_BATCH),
 203       .cache = (CACHE_NEW_SAMPLER |
 204                 CACHE_NEW_WM_PROG)
 205    },
 206    .emit = upload_ps_state,
 207 };