src/mesa/drivers/dri/i965/gen7_wm_state.c

   1 /*
   2  * Copyright © 2011 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include <stdbool.h>
  25 #include "brw_context.h"
  26 #include "brw_state.h"
  27 #include "brw_defines.h"
  28 #include "brw_util.h"
  29 #include "brw_wm.h"
  30 #include "program/prog_parameter.h"
  31 #include "program/prog_statevars.h"
  32 #include "intel_batchbuffer.h"
  33
  34 static void
  35 upload_wm_state(struct brw_context *brw)
  36 {
  37    struct gl_context *ctx = &brw->ctx;
  38    const struct brw_fragment_program *fp =
  39       brw_fragment_program_const(brw->fragment_program);
  40    bool writes_depth = false;
  41    uint32_t dw1, dw2;
  42
  43    /* _NEW_BUFFERS */
  44    bool multisampled_fbo = ctx->DrawBuffer->Visual.samples > 1;
  45
  46    dw1 = dw2 = 0;
  47    dw1 |= GEN7_WM_STATISTICS_ENABLE;
  48    dw1 |= GEN7_WM_LINE_AA_WIDTH_1_0;
  49    dw1 |= GEN7_WM_LINE_END_CAP_AA_WIDTH_0_5;
  50
  51    /* _NEW_LINE */
  52    if (ctx->Line.StippleFlag)
  53       dw1 |= GEN7_WM_LINE_STIPPLE_ENABLE;
  54
  55    /* _NEW_POLYGON */
  56    if (ctx->Polygon.StippleFlag)
  57       dw1 |= GEN7_WM_POLYGON_STIPPLE_ENABLE;
  58
  59    /* BRW_NEW_FRAGMENT_PROGRAM */
  60    if (fp->program.Base.InputsRead & VARYING_BIT_POS)
  61       dw1 |= GEN7_WM_USES_SOURCE_DEPTH | GEN7_WM_USES_SOURCE_W;
  62    if (fp->program.Base.OutputsWritten & BITFIELD64_BIT(FRAG_RESULT_DEPTH)) {
  63       writes_depth = fp->program.FragDepthLayout != FRAG_DEPTH_LAYOUT_UNCHANGED;
  64
  65       switch (fp->program.FragDepthLayout) {
  66          case FRAG_DEPTH_LAYOUT_NONE:
  67          case FRAG_DEPTH_LAYOUT_ANY:
  68             dw1 |= GEN7_WM_PSCDEPTH_ON;
  69             break;
  70          case FRAG_DEPTH_LAYOUT_GREATER:
  71             dw1 |= GEN7_WM_PSCDEPTH_ON_GE;
  72             break;
  73          case FRAG_DEPTH_LAYOUT_LESS:
  74             dw1 |= GEN7_WM_PSCDEPTH_ON_LE;
  75             break;
  76          case FRAG_DEPTH_LAYOUT_UNCHANGED:
  77             break;
  78       }
  79    }
  80    /* CACHE_NEW_WM_PROG */
  81    dw1 |= brw->wm.prog_data->barycentric_interp_modes <<
  82       GEN7_WM_BARYCENTRIC_INTERPOLATION_MODE_SHIFT;
  83
  84    /* _NEW_COLOR, _NEW_MULTISAMPLE */
  85    if (fp->program.UsesKill || ctx->Color.AlphaEnabled ||
  86        ctx->Multisample.SampleAlphaToCoverage)
  87       dw1 |= GEN7_WM_KILL_ENABLE;
  88
  89    /* _NEW_BUFFERS */
  90    if (brw_color_buffer_write_enabled(brw) || writes_depth ||
  91        dw1 & GEN7_WM_KILL_ENABLE) {
  92       dw1 |= GEN7_WM_DISPATCH_ENABLE;
  93    }
  94    if (multisampled_fbo) {
  95       /* _NEW_MULTISAMPLE */
  96       if (ctx->Multisample.Enabled)
  97          dw1 |= GEN7_WM_MSRAST_ON_PATTERN;
  98       else
  99          dw1 |= GEN7_WM_MSRAST_OFF_PIXEL;
 100       dw2 |= GEN7_WM_MSDISPMODE_PERPIXEL;
 101    } else {
 102       dw1 |= GEN7_WM_MSRAST_OFF_PIXEL;
 103       dw2 |= GEN7_WM_MSDISPMODE_PERSAMPLE;
 104    }
 105
 106    BEGIN_BATCH(3);
 107    OUT_BATCH(_3DSTATE_WM << 16 | (3 - 2));
 108    OUT_BATCH(dw1);
 109    OUT_BATCH(dw2);
 110    ADVANCE_BATCH();
 111 }
 112
 113 const struct brw_tracked_state gen7_wm_state = {
 114    .dirty = {
 115       .mesa  = (_NEW_LINE | _NEW_POLYGON |
 116                 _NEW_COLOR | _NEW_BUFFERS |
 117                 _NEW_MULTISAMPLE),
 118       .brw   = (BRW_NEW_FRAGMENT_PROGRAM |
 119                 BRW_NEW_BATCH),
 120       .cache = CACHE_NEW_WM_PROG,
 121    },
 122    .emit = upload_wm_state,
 123 };
 124
 125 static void
 126 upload_ps_state(struct brw_context *brw)
 127 {
 128    struct gl_context *ctx = &brw->ctx;
 129    uint32_t dw2, dw4, dw5;
 130    const int max_threads_shift = brw->is_haswell ?
 131       HSW_PS_MAX_THREADS_SHIFT : IVB_PS_MAX_THREADS_SHIFT;
 132
 133    /* BRW_NEW_PS_BINDING_TABLE */
 134    BEGIN_BATCH(2);
 135    OUT_BATCH(_3DSTATE_BINDING_TABLE_POINTERS_PS << 16 | (2 - 2));
 136    OUT_BATCH(brw->wm.base.bind_bo_offset);
 137    ADVANCE_BATCH();
 138
 139    /* CACHE_NEW_SAMPLER */
 140    BEGIN_BATCH(2);
 141    OUT_BATCH(_3DSTATE_SAMPLER_STATE_POINTERS_PS << 16 | (2 - 2));
 142    OUT_BATCH(brw->wm.base.sampler_offset);
 143    ADVANCE_BATCH();
 144
 145    /* CACHE_NEW_WM_PROG */
 146    gen7_upload_constant_state(brw, &brw->wm.base, true, _3DSTATE_CONSTANT_PS);
 147
 148    dw2 = dw4 = dw5 = 0;
 149
 150    /* CACHE_NEW_SAMPLER */
 151    dw2 |=
 152       (ALIGN(brw->wm.base.sampler_count, 4) / 4) << GEN7_PS_SAMPLER_COUNT_SHIFT;
 153
 154    /* Use ALT floating point mode for ARB fragment programs, because they
 155     * require 0^0 == 1.  Even though _CurrentFragmentProgram is used for
 156     * rendering, CurrentFragmentProgram is used for this check to
 157     * differentiate between the GLSL and non-GLSL cases.
 158     */
 159    /* BRW_NEW_FRAGMENT_PROGRAM */
 160    if (ctx->Shader.CurrentFragmentProgram == NULL)
 161       dw2 |= GEN7_PS_FLOATING_POINT_MODE_ALT;
 162
 163    if (brw->is_haswell)
 164       dw4 |= SET_FIELD(1, HSW_PS_SAMPLE_MASK); /* 1 sample for now */
 165
 166    dw4 |= (brw->max_wm_threads - 1) << max_threads_shift;
 167
 168    /* CACHE_NEW_WM_PROG */
 169    if (brw->wm.prog_data->nr_params > 0)
 170       dw4 |= GEN7_PS_PUSH_CONSTANT_ENABLE;
 171
 172    /* CACHE_NEW_WM_PROG | _NEW_COLOR
 173     *
 174     * The hardware wedges if you have this bit set but don't turn on any dual
 175     * source blend factors.
 176     */
 177    if (brw->wm.prog_data->dual_src_blend &&
 178        (ctx->Color.BlendEnabled & 1) &&
 179        ctx->Color.Blend[0]._UsesDualSrc) {
 180       dw4 |= GEN7_PS_DUAL_SOURCE_BLEND_ENABLE;
 181    }
 182
 183    /* CACHE_NEW_WM_PROG */
 184    if (brw->wm.prog_data->num_varying_inputs != 0)
 185       dw4 |= GEN7_PS_ATTRIBUTE_ENABLE;
 186
 187    dw4 |= GEN7_PS_8_DISPATCH_ENABLE;
 188    if (brw->wm.prog_data->prog_offset_16)
 189       dw4 |= GEN7_PS_16_DISPATCH_ENABLE;
 190
 191    dw5 |= (brw->wm.prog_data->first_curbe_grf <<
 192            GEN7_PS_DISPATCH_START_GRF_SHIFT_0);
 193    dw5 |= (brw->wm.prog_data->first_curbe_grf_16 <<
 194            GEN7_PS_DISPATCH_START_GRF_SHIFT_2);
 195
 196    BEGIN_BATCH(8);
 197    OUT_BATCH(_3DSTATE_PS << 16 | (8 - 2));
 198    OUT_BATCH(brw->wm.base.prog_offset);
 199    OUT_BATCH(dw2);
 200    if (brw->wm.prog_data->total_scratch) {
 201       OUT_RELOC(brw->wm.base.scratch_bo,
 202                 I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
 203                 ffs(brw->wm.prog_data->total_scratch) - 11);
 204    } else {
 205       OUT_BATCH(0);
 206    }
 207    OUT_BATCH(dw4);
 208    OUT_BATCH(dw5);
 209    OUT_BATCH(0); /* kernel 1 pointer */
 210    OUT_BATCH(brw->wm.base.prog_offset + brw->wm.prog_data->prog_offset_16);
 211    ADVANCE_BATCH();
 212 }
 213
 214 const struct brw_tracked_state gen7_ps_state = {
 215    .dirty = {
 216       .mesa  = (_NEW_PROGRAM_CONSTANTS |
 217                 _NEW_COLOR),
 218       .brw   = (BRW_NEW_FRAGMENT_PROGRAM |
 219                 BRW_NEW_PS_BINDING_TABLE |
 220                 BRW_NEW_BATCH |
 221                 BRW_NEW_PUSH_CONSTANT_ALLOCATION),
 222       .cache = (CACHE_NEW_SAMPLER |
 223                 CACHE_NEW_WM_PROG)
 224    },
 225    .emit = upload_ps_state,
 226 };