src/mesa/drivers/dri/i965/gen7_wm_state.c

   1 /*
   2  * Copyright © 2011 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include <stdbool.h>
  25 #include "brw_context.h"
  26 #include "brw_state.h"
  27 #include "brw_defines.h"
  28 #include "brw_util.h"
  29 #include "brw_wm.h"
  30 #include "program/program.h"
  31 #include "program/prog_parameter.h"
  32 #include "program/prog_statevars.h"
  33 #include "intel_batchbuffer.h"
  34
  35 static void
  36 upload_wm_state(struct brw_context *brw)
  37 {
  38    struct gl_context *ctx = &brw->ctx;
  39    const struct brw_fragment_program *fp =
  40       brw_fragment_program_const(brw->fragment_program);
  41    bool writes_depth = false;
  42    uint32_t dw1, dw2;
  43
  44    /* _NEW_BUFFERS */
  45    bool multisampled_fbo = ctx->DrawBuffer->Visual.samples > 1;
  46
  47    dw1 = dw2 = 0;
  48    dw1 |= GEN7_WM_STATISTICS_ENABLE;
  49    dw1 |= GEN7_WM_LINE_AA_WIDTH_1_0;
  50    dw1 |= GEN7_WM_LINE_END_CAP_AA_WIDTH_0_5;
  51
  52    /* _NEW_LINE */
  53    if (ctx->Line.StippleFlag)
  54       dw1 |= GEN7_WM_LINE_STIPPLE_ENABLE;
  55
  56    /* _NEW_POLYGON */
  57    if (ctx->Polygon.StippleFlag)
  58       dw1 |= GEN7_WM_POLYGON_STIPPLE_ENABLE;
  59
  60    /* BRW_NEW_FRAGMENT_PROGRAM */
  61    if (fp->program.Base.InputsRead & VARYING_BIT_POS)
  62       dw1 |= GEN7_WM_USES_SOURCE_DEPTH | GEN7_WM_USES_SOURCE_W;
  63    if (fp->program.Base.OutputsWritten & BITFIELD64_BIT(FRAG_RESULT_DEPTH)) {
  64       writes_depth = fp->program.FragDepthLayout != FRAG_DEPTH_LAYOUT_UNCHANGED;
  65
  66       switch (fp->program.FragDepthLayout) {
  67          case FRAG_DEPTH_LAYOUT_NONE:
  68          case FRAG_DEPTH_LAYOUT_ANY:
  69             dw1 |= GEN7_WM_PSCDEPTH_ON;
  70             break;
  71          case FRAG_DEPTH_LAYOUT_GREATER:
  72             dw1 |= GEN7_WM_PSCDEPTH_ON_GE;
  73             break;
  74          case FRAG_DEPTH_LAYOUT_LESS:
  75             dw1 |= GEN7_WM_PSCDEPTH_ON_LE;
  76             break;
  77          case FRAG_DEPTH_LAYOUT_UNCHANGED:
  78             break;
  79       }
  80    }
  81    /* CACHE_NEW_WM_PROG */
  82    dw1 |= brw->wm.prog_data->barycentric_interp_modes <<
  83       GEN7_WM_BARYCENTRIC_INTERPOLATION_MODE_SHIFT;
  84
  85    /* _NEW_COLOR, _NEW_MULTISAMPLE */
  86    /* Enable if the pixel shader kernel generates and outputs oMask.
  87     */
  88    if (fp->program.UsesKill || ctx->Color.AlphaEnabled ||
  89        ctx->Multisample.SampleAlphaToCoverage ||
  90        brw->wm.prog_data->uses_omask) {
  91       dw1 |= GEN7_WM_KILL_ENABLE;
  92    }
  93
  94    /* _NEW_BUFFERS */
  95    if (brw_color_buffer_write_enabled(brw) || writes_depth ||
  96        dw1 & GEN7_WM_KILL_ENABLE) {
  97       dw1 |= GEN7_WM_DISPATCH_ENABLE;
  98    }
  99    if (multisampled_fbo) {
 100       /* _NEW_MULTISAMPLE */
 101       if (ctx->Multisample.Enabled)
 102          dw1 |= GEN7_WM_MSRAST_ON_PATTERN;
 103       else
 104          dw1 |= GEN7_WM_MSRAST_OFF_PIXEL;
 105
 106       if (_mesa_get_min_invocations_per_fragment(ctx, brw->fragment_program) > 1)
 107          dw2 |= GEN7_WM_MSDISPMODE_PERSAMPLE;
 108       else
 109          dw2 |= GEN7_WM_MSDISPMODE_PERPIXEL;
 110    } else {
 111       dw1 |= GEN7_WM_MSRAST_OFF_PIXEL;
 112       dw2 |= GEN7_WM_MSDISPMODE_PERSAMPLE;
 113    }
 114
 115    BEGIN_BATCH(3);
 116    OUT_BATCH(_3DSTATE_WM << 16 | (3 - 2));
 117    OUT_BATCH(dw1);
 118    OUT_BATCH(dw2);
 119    ADVANCE_BATCH();
 120 }
 121
 122 const struct brw_tracked_state gen7_wm_state = {
 123    .dirty = {
 124       .mesa  = (_NEW_LINE | _NEW_POLYGON |
 125                 _NEW_COLOR | _NEW_BUFFERS |
 126                 _NEW_MULTISAMPLE),
 127       .brw   = (BRW_NEW_FRAGMENT_PROGRAM |
 128                 BRW_NEW_BATCH),
 129       .cache = CACHE_NEW_WM_PROG,
 130    },
 131    .emit = upload_wm_state,
 132 };
 133
 134 static void
 135 upload_ps_state(struct brw_context *brw)
 136 {
 137    struct gl_context *ctx = &brw->ctx;
 138    uint32_t dw2, dw4, dw5;
 139    const int max_threads_shift = brw->is_haswell ?
 140       HSW_PS_MAX_THREADS_SHIFT : IVB_PS_MAX_THREADS_SHIFT;
 141
 142    /* BRW_NEW_PS_BINDING_TABLE */
 143    BEGIN_BATCH(2);
 144    OUT_BATCH(_3DSTATE_BINDING_TABLE_POINTERS_PS << 16 | (2 - 2));
 145    OUT_BATCH(brw->wm.base.bind_bo_offset);
 146    ADVANCE_BATCH();
 147
 148    /* CACHE_NEW_SAMPLER */
 149    BEGIN_BATCH(2);
 150    OUT_BATCH(_3DSTATE_SAMPLER_STATE_POINTERS_PS << 16 | (2 - 2));
 151    OUT_BATCH(brw->wm.base.sampler_offset);
 152    ADVANCE_BATCH();
 153
 154    /* CACHE_NEW_WM_PROG */
 155    gen7_upload_constant_state(brw, &brw->wm.base, true, _3DSTATE_CONSTANT_PS);
 156
 157    dw2 = dw4 = dw5 = 0;
 158
 159    /* CACHE_NEW_SAMPLER */
 160    dw2 |=
 161       (ALIGN(brw->wm.base.sampler_count, 4) / 4) << GEN7_PS_SAMPLER_COUNT_SHIFT;
 162
 163    /* CACHE_NEW_WM_PROG */
 164    dw2 |= ((brw->wm.prog_data->base.binding_table.size_bytes / 4) <<
 165            GEN7_PS_BINDING_TABLE_ENTRY_COUNT_SHIFT);
 166
 167    /* Use ALT floating point mode for ARB fragment programs, because they
 168     * require 0^0 == 1.  Even though _CurrentFragmentProgram is used for
 169     * rendering, CurrentFragmentProgram is used for this check to
 170     * differentiate between the GLSL and non-GLSL cases.
 171     */
 172    /* BRW_NEW_FRAGMENT_PROGRAM */
 173    if (ctx->Shader.CurrentFragmentProgram == NULL)
 174       dw2 |= GEN7_PS_FLOATING_POINT_MODE_ALT;
 175
 176    /* Haswell requires the sample mask to be set in this packet as well as
 177     * in 3DSTATE_SAMPLE_MASK; the values should match. */
 178    /* _NEW_BUFFERS, _NEW_MULTISAMPLE */
 179    if (brw->is_haswell)
 180       dw4 |= SET_FIELD(gen6_determine_sample_mask(brw), HSW_PS_SAMPLE_MASK);
 181
 182    dw4 |= (brw->max_wm_threads - 1) << max_threads_shift;
 183
 184    /* CACHE_NEW_WM_PROG */
 185    if (brw->wm.prog_data->nr_params > 0)
 186       dw4 |= GEN7_PS_PUSH_CONSTANT_ENABLE;
 187
 188    /* From the IVB PRM, volume 2 part 1, page 287:
 189     * "This bit is inserted in the PS payload header and made available to
 190     * the DataPort (either via the message header or via header bypass) to
 191     * indicate that oMask data (one or two phases) is included in Render
 192     * Target Write messages. If present, the oMask data is used to mask off
 193     * samples."
 194     */
 195    if (brw->wm.prog_data->uses_omask)
 196       dw4 |= GEN7_PS_OMASK_TO_RENDER_TARGET;
 197
 198    /* From the IVB PRM, volume 2 part 1, page 287:
 199     * "If the PS kernel does not need the Position XY Offsets to
 200     * compute a Position Value, then this field should be programmed
 201     * to POSOFFSET_NONE."
 202     * "SW Recommendation: If the PS kernel needs the Position Offsets
 203     * to compute a Position XY value, this field should match Position
 204     * ZW Interpolation Mode to ensure a consistent position.xyzw
 205     * computation."
 206     * We only require XY sample offsets. So, this recommendation doesn't
 207     * look useful at the moment. We might need this in future.
 208     */
 209    if (brw->wm.prog_data->uses_pos_offset)
 210       dw4 |= GEN7_PS_POSOFFSET_SAMPLE;
 211    else
 212       dw4 |= GEN7_PS_POSOFFSET_NONE;
 213
 214    /* CACHE_NEW_WM_PROG | _NEW_COLOR
 215     *
 216     * The hardware wedges if you have this bit set but don't turn on any dual
 217     * source blend factors.
 218     */
 219    if (brw->wm.prog_data->dual_src_blend &&
 220        (ctx->Color.BlendEnabled & 1) &&
 221        ctx->Color.Blend[0]._UsesDualSrc) {
 222       dw4 |= GEN7_PS_DUAL_SOURCE_BLEND_ENABLE;
 223    }
 224
 225    /* CACHE_NEW_WM_PROG */
 226    if (brw->wm.prog_data->num_varying_inputs != 0)
 227       dw4 |= GEN7_PS_ATTRIBUTE_ENABLE;
 228
 229    /* In case of non 1x per sample shading, only one of SIMD8 and SIMD16
 230     * should be enabled. We do 'SIMD16 only' dispatch if a SIMD16 shader
 231     * is successfully compiled. In majority of the cases that bring us
 232     * better performance than 'SIMD8 only' dispatch.
 233     */
 234    int min_inv_per_frag =
 235       _mesa_get_min_invocations_per_fragment(ctx, brw->fragment_program);
 236    assert(min_inv_per_frag >= 1);
 237
 238    if (brw->wm.prog_data->prog_offset_16) {
 239       dw4 |= GEN7_PS_16_DISPATCH_ENABLE;
 240       if (min_inv_per_frag == 1) {
 241          dw4 |= GEN7_PS_8_DISPATCH_ENABLE;
 242          dw5 |= (brw->wm.prog_data->first_curbe_grf <<
 243                  GEN7_PS_DISPATCH_START_GRF_SHIFT_0);
 244          dw5 |= (brw->wm.prog_data->first_curbe_grf_16 <<
 245                  GEN7_PS_DISPATCH_START_GRF_SHIFT_2);
 246       } else
 247          dw5 |= (brw->wm.prog_data->first_curbe_grf_16 <<
 248                  GEN7_PS_DISPATCH_START_GRF_SHIFT_0);
 249    }
 250    else {
 251       dw4 |= GEN7_PS_8_DISPATCH_ENABLE;
 252       dw5 |= (brw->wm.prog_data->first_curbe_grf <<
 253               GEN7_PS_DISPATCH_START_GRF_SHIFT_0);
 254    }
 255
 256    BEGIN_BATCH(8);
 257    OUT_BATCH(_3DSTATE_PS << 16 | (8 - 2));
 258    if (brw->wm.prog_data->prog_offset_16 && min_inv_per_frag > 1)
 259       OUT_BATCH(brw->wm.base.prog_offset + brw->wm.prog_data->prog_offset_16);
 260    else
 261       OUT_BATCH(brw->wm.base.prog_offset);
 262    OUT_BATCH(dw2);
 263    if (brw->wm.prog_data->total_scratch) {
 264       OUT_RELOC(brw->wm.base.scratch_bo,
 265                 I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
 266                 ffs(brw->wm.prog_data->total_scratch) - 11);
 267    } else {
 268       OUT_BATCH(0);
 269    }
 270    OUT_BATCH(dw4);
 271    OUT_BATCH(dw5);
 272    OUT_BATCH(0); /* kernel 1 pointer */
 273    OUT_BATCH(brw->wm.base.prog_offset + brw->wm.prog_data->prog_offset_16);
 274    ADVANCE_BATCH();
 275 }
 276
 277 const struct brw_tracked_state gen7_ps_state = {
 278    .dirty = {
 279       .mesa  = (_NEW_PROGRAM_CONSTANTS |
 280                 _NEW_COLOR |
 281                 _NEW_BUFFERS |
 282                 _NEW_MULTISAMPLE),
 283       .brw   = (BRW_NEW_FRAGMENT_PROGRAM |
 284                 BRW_NEW_PS_BINDING_TABLE |
 285                 BRW_NEW_BATCH |
 286                 BRW_NEW_PUSH_CONSTANT_ALLOCATION),
 287       .cache = (CACHE_NEW_SAMPLER |
 288                 CACHE_NEW_WM_PROG)
 289    },
 290    .emit = upload_ps_state,
 291 };