src/mesa/drivers/dri/i965/gen7_wm_state.c

   1 /*
   2  * Copyright © 2011 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include <stdbool.h>
  25 #include "brw_context.h"
  26 #include "brw_state.h"
  27 #include "brw_defines.h"
  28 #include "brw_util.h"
  29 #include "brw_wm.h"
  30 #include "program/prog_parameter.h"
  31 #include "program/prog_statevars.h"
  32 #include "intel_batchbuffer.h"
  33
  34 static void
  35 gen7_prepare_wm_constants(struct brw_context *brw)
  36 {
  37    struct intel_context *intel = &brw->intel;
  38    struct gl_context *ctx = &intel->ctx;
  39    const struct brw_fragment_program *fp =
  40       brw_fragment_program_const(brw->fragment_program);
  41
  42    /* Updates the ParameterValues[i] pointers for all parameters of the
  43     * basic type of PROGRAM_STATE_VAR.
  44     */
  45    /* XXX: Should this happen somewhere before to get our state flag set? */
  46    _mesa_load_state_parameters(ctx, fp->program.Base.Parameters);
  47
  48    /* BRW_NEW_FRAGMENT_PROGRAM */
  49    if (brw->wm.prog_data->nr_params != 0) {
  50       float *constants;
  51       unsigned int i;
  52
  53       constants = brw_state_batch(brw,
  54                                   brw->wm.prog_data->nr_params *
  55                                   sizeof(float),
  56                                   32, &brw->wm.push_const_offset);
  57
  58       for (i = 0; i < brw->wm.prog_data->nr_params; i++) {
  59          constants[i] = convert_param(brw->wm.prog_data->param_convert[i],
  60                                       *brw->wm.prog_data->param[i]);
  61       }
  62
  63       if (0) {
  64          printf("WM constants:\n");
  65          for (i = 0; i < brw->wm.prog_data->nr_params; i++) {
  66             if ((i & 7) == 0)
  67                printf("g%d: ", brw->wm.prog_data->first_curbe_grf + i / 8);
  68             printf("%8f ", constants[i]);
  69             if ((i & 7) == 7)
  70                printf("\n");
  71          }
  72          if ((i & 7) != 0)
  73             printf("\n");
  74          printf("\n");
  75       }
  76    }
  77 }
  78
  79 const struct brw_tracked_state gen7_wm_constants = {
  80    .dirty = {
  81       .mesa  = _NEW_PROGRAM_CONSTANTS,
  82       .brw   = (BRW_NEW_BATCH | BRW_NEW_FRAGMENT_PROGRAM),
  83       .cache = 0,
  84    },
  85    .prepare = gen7_prepare_wm_constants,
  86 };
  87
  88 static void
  89 upload_wm_state(struct brw_context *brw)
  90 {
  91    struct intel_context *intel = &brw->intel;
  92    struct gl_context *ctx = &intel->ctx;
  93    const struct brw_fragment_program *fp =
  94       brw_fragment_program_const(brw->fragment_program);
  95    bool writes_depth = false;
  96    uint32_t dw1;
  97
  98    dw1 = 0;
  99    dw1 |= GEN7_WM_STATISTICS_ENABLE;
 100    dw1 |= GEN7_WM_LINE_AA_WIDTH_1_0;
 101    dw1 |= GEN7_WM_LINE_END_CAP_AA_WIDTH_0_5;
 102
 103    /* _NEW_LINE */
 104    if (ctx->Line.StippleFlag)
 105       dw1 |= GEN7_WM_LINE_STIPPLE_ENABLE;
 106
 107    /* _NEW_POLYGONSTIPPLE */
 108    if (ctx->Polygon.StippleFlag)
 109       dw1 |= GEN7_WM_POLYGON_STIPPLE_ENABLE;
 110
 111    /* BRW_NEW_FRAGMENT_PROGRAM */
 112    if (fp->program.Base.InputsRead & (1 << FRAG_ATTRIB_WPOS))
 113       dw1 |= GEN7_WM_USES_SOURCE_DEPTH | GEN7_WM_USES_SOURCE_W;
 114    if (fp->program.Base.OutputsWritten & BITFIELD64_BIT(FRAG_RESULT_DEPTH)) {
 115       writes_depth = true;
 116       dw1 |= GEN7_WM_PSCDEPTH_ON;
 117    }
 118
 119    /* _NEW_COLOR */
 120    if (fp->program.UsesKill || ctx->Color.AlphaEnabled)
 121       dw1 |= GEN7_WM_KILL_ENABLE;
 122
 123    /* _NEW_BUFFERS */
 124    if (brw_color_buffer_write_enabled(brw) || writes_depth ||
 125        dw1 & GEN7_WM_KILL_ENABLE) {
 126       dw1 |= GEN7_WM_DISPATCH_ENABLE;
 127    }
 128
 129    dw1 |= GEN7_WM_PERSPECTIVE_PIXEL_BARYCENTRIC;
 130
 131    BEGIN_BATCH(3);
 132    OUT_BATCH(_3DSTATE_WM << 16 | (3 - 2));
 133    OUT_BATCH(dw1);
 134    OUT_BATCH(0);
 135    ADVANCE_BATCH();
 136 }
 137
 138 const struct brw_tracked_state gen7_wm_state = {
 139    .dirty = {
 140       .mesa  = (_NEW_LINE | _NEW_POLYGON | _NEW_POLYGONSTIPPLE |
 141                 _NEW_COLOR | _NEW_BUFFERS),
 142       .brw   = (BRW_NEW_CURBE_OFFSETS |
 143                 BRW_NEW_FRAGMENT_PROGRAM |
 144                 BRW_NEW_NR_WM_SURFACES |
 145                 BRW_NEW_URB_FENCE |
 146                 BRW_NEW_BATCH),
 147       .cache = 0,
 148    },
 149    .emit = upload_wm_state,
 150 };
 151
 152 static void
 153 upload_ps_state(struct brw_context *brw)
 154 {
 155    struct intel_context *intel = &brw->intel;
 156    uint32_t dw2, dw4, dw5;
 157
 158    BEGIN_BATCH(2);
 159    OUT_BATCH(_3DSTATE_BINDING_TABLE_POINTERS_PS << 16 | (2 - 2));
 160    OUT_BATCH(brw->wm.bind_bo_offset);
 161    ADVANCE_BATCH();
 162
 163    /* CACHE_NEW_SAMPLER */
 164    BEGIN_BATCH(2);
 165    OUT_BATCH(_3DSTATE_SAMPLER_STATE_POINTERS_PS << 16 | (2 - 2));
 166    OUT_BATCH(brw->wm.sampler_offset);
 167    ADVANCE_BATCH();
 168
 169    /* CACHE_NEW_WM_PROG */
 170    if (brw->wm.prog_data->nr_params == 0) {
 171       /* Disable the push constant buffers. */
 172       BEGIN_BATCH(7);
 173       OUT_BATCH(_3DSTATE_CONSTANT_PS << 16 | (7 - 2));
 174       OUT_BATCH(0);
 175       OUT_BATCH(0);
 176       OUT_BATCH(0);
 177       OUT_BATCH(0);
 178       OUT_BATCH(0);
 179       OUT_BATCH(0);
 180       ADVANCE_BATCH();
 181    } else {
 182       BEGIN_BATCH(7);
 183       OUT_BATCH(_3DSTATE_CONSTANT_PS << 16 | (7 - 2));
 184
 185       OUT_BATCH(ALIGN(brw->wm.prog_data->nr_params,
 186                       brw->wm.prog_data->dispatch_width) / 8);
 187       OUT_BATCH(0);
 188       /* Pointer to the WM constant buffer.  Covered by the set of
 189        * state flags from gen7_prepare_wm_constants
 190        */
 191       OUT_BATCH(brw->wm.push_const_offset);
 192       OUT_BATCH(0);
 193       OUT_BATCH(0);
 194       OUT_BATCH(0);
 195       ADVANCE_BATCH();
 196    }
 197
 198    dw2 = dw4 = dw5 = 0;
 199
 200    dw2 |= (ALIGN(brw->wm.sampler_count, 4) / 4) << GEN7_PS_SAMPLER_COUNT_SHIFT;
 201
 202    /* BRW_NEW_NR_WM_SURFACES */
 203    dw2 |= brw->wm.nr_surfaces << GEN7_PS_BINDING_TABLE_ENTRY_COUNT_SHIFT;
 204
 205    /* OpenGL non-ieee floating point mode */
 206    dw2 |= GEN7_PS_FLOATING_POINT_MODE_ALT;
 207
 208    /* CACHE_NEW_SAMPLER */
 209    dw4 |= (brw->wm_max_threads - 1) << GEN7_PS_MAX_THREADS_SHIFT;
 210
 211    /* CACHE_NEW_WM_PROG */
 212    if (brw->wm.prog_data->nr_params > 0)
 213       dw4 |= GEN7_PS_PUSH_CONSTANT_ENABLE;
 214
 215    /* BRW_NEW_FRAGMENT_PROGRAM */
 216    if (brw->fragment_program->Base.InputsRead != 0)
 217       dw4 |= GEN7_PS_ATTRIBUTE_ENABLE;
 218
 219    if (brw->wm.prog_data->dispatch_width == 8)
 220       dw4 |= GEN7_PS_8_DISPATCH_ENABLE;
 221    else
 222       dw4 |= GEN7_PS_16_DISPATCH_ENABLE;
 223
 224    /* BRW_NEW_CURBE_OFFSETS */
 225    dw5 |= (brw->wm.prog_data->first_curbe_grf <<
 226            GEN7_PS_DISPATCH_START_GRF_SHIFT_0);
 227
 228    BEGIN_BATCH(8);
 229    OUT_BATCH(_3DSTATE_PS << 16 | (8 - 2));
 230    OUT_BATCH(brw->wm.prog_offset);
 231    OUT_BATCH(dw2);
 232    OUT_BATCH(0); /* scratch space base offset */
 233    OUT_BATCH(dw4);
 234    OUT_BATCH(dw5);
 235    OUT_BATCH(0); /* kernel 1 pointer */
 236    OUT_BATCH(brw->wm.prog_offset + brw->wm.prog_data->prog_offset_16);
 237    ADVANCE_BATCH();
 238 }
 239
 240 const struct brw_tracked_state gen7_ps_state = {
 241    .dirty = {
 242       .mesa  = (_NEW_LINE | _NEW_POLYGON | _NEW_POLYGONSTIPPLE |
 243                 _NEW_PROGRAM_CONSTANTS),
 244       .brw   = (BRW_NEW_CURBE_OFFSETS |
 245                 BRW_NEW_FRAGMENT_PROGRAM |
 246                 BRW_NEW_NR_WM_SURFACES |
 247                 BRW_NEW_PS_BINDING_TABLE |
 248                 BRW_NEW_URB_FENCE |
 249                 BRW_NEW_BATCH),
 250       .cache = (CACHE_NEW_SAMPLER |
 251                 CACHE_NEW_WM_PROG)
 252    },
 253    .emit = upload_ps_state,
 254 };