src/mesa/drivers/dri/i965/gen7_wm_state.c

   1 /*
   2  * Copyright © 2011 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include <stdbool.h>
  25 #include "brw_context.h"
  26 #include "brw_state.h"
  27 #include "brw_defines.h"
  28 #include "brw_util.h"
  29 #include "brw_wm.h"
  30 #include "program/prog_parameter.h"
  31 #include "program/prog_statevars.h"
  32 #include "intel_batchbuffer.h"
  33
  34 static void
  35 upload_wm_state(struct brw_context *brw)
  36 {
  37    struct intel_context *intel = &brw->intel;
  38    struct gl_context *ctx = &intel->ctx;
  39    const struct brw_fragment_program *fp =
  40       brw_fragment_program_const(brw->fragment_program);
  41    bool writes_depth = false;
  42    uint32_t dw1, dw2;
  43
  44    /* _NEW_BUFFERS */
  45    bool multisampled_fbo = ctx->DrawBuffer->Visual.samples > 1;
  46
  47    dw1 = dw2 = 0;
  48    dw1 |= GEN7_WM_STATISTICS_ENABLE;
  49    dw1 |= GEN7_WM_LINE_AA_WIDTH_1_0;
  50    dw1 |= GEN7_WM_LINE_END_CAP_AA_WIDTH_0_5;
  51
  52    /* _NEW_LINE */
  53    if (ctx->Line.StippleFlag)
  54       dw1 |= GEN7_WM_LINE_STIPPLE_ENABLE;
  55
  56    /* _NEW_POLYGON */
  57    if (ctx->Polygon.StippleFlag)
  58       dw1 |= GEN7_WM_POLYGON_STIPPLE_ENABLE;
  59
  60    /* BRW_NEW_FRAGMENT_PROGRAM */
  61    if (fp->program.Base.InputsRead & VARYING_BIT_POS)
  62       dw1 |= GEN7_WM_USES_SOURCE_DEPTH | GEN7_WM_USES_SOURCE_W;
  63    if (fp->program.Base.OutputsWritten & BITFIELD64_BIT(FRAG_RESULT_DEPTH)) {
  64       writes_depth = true;
  65       dw1 |= GEN7_WM_PSCDEPTH_ON;
  66    }
  67    /* CACHE_NEW_WM_PROG */
  68    dw1 |= brw->wm.prog_data->barycentric_interp_modes <<
  69       GEN7_WM_BARYCENTRIC_INTERPOLATION_MODE_SHIFT;
  70
  71    /* _NEW_COLOR, _NEW_MULTISAMPLE */
  72    if (fp->program.UsesKill || ctx->Color.AlphaEnabled ||
  73        ctx->Multisample.SampleAlphaToCoverage)
  74       dw1 |= GEN7_WM_KILL_ENABLE;
  75
  76    /* _NEW_BUFFERS */
  77    if (brw_color_buffer_write_enabled(brw) || writes_depth ||
  78        dw1 & GEN7_WM_KILL_ENABLE) {
  79       dw1 |= GEN7_WM_DISPATCH_ENABLE;
  80    }
  81    if (multisampled_fbo) {
  82       /* _NEW_MULTISAMPLE */
  83       if (ctx->Multisample.Enabled)
  84          dw1 |= GEN7_WM_MSRAST_ON_PATTERN;
  85       else
  86          dw1 |= GEN7_WM_MSRAST_OFF_PIXEL;
  87       dw2 |= GEN7_WM_MSDISPMODE_PERPIXEL;
  88    } else {
  89       dw1 |= GEN7_WM_MSRAST_OFF_PIXEL;
  90       dw2 |= GEN7_WM_MSDISPMODE_PERSAMPLE;
  91    }
  92
  93    BEGIN_BATCH(3);
  94    OUT_BATCH(_3DSTATE_WM << 16 | (3 - 2));
  95    OUT_BATCH(dw1);
  96    OUT_BATCH(dw2);
  97    ADVANCE_BATCH();
  98 }
  99
 100 const struct brw_tracked_state gen7_wm_state = {
 101    .dirty = {
 102       .mesa  = (_NEW_LINE | _NEW_POLYGON |
 103                 _NEW_COLOR | _NEW_BUFFERS |
 104                 _NEW_MULTISAMPLE),
 105       .brw   = (BRW_NEW_FRAGMENT_PROGRAM |
 106                 BRW_NEW_BATCH),
 107       .cache = CACHE_NEW_WM_PROG,
 108    },
 109    .emit = upload_wm_state,
 110 };
 111
 112 static void
 113 upload_ps_state(struct brw_context *brw)
 114 {
 115    struct intel_context *intel = &brw->intel;
 116    struct gl_context *ctx = &intel->ctx;
 117    uint32_t dw2, dw4, dw5;
 118    const int max_threads_shift = brw->intel.is_haswell ?
 119       HSW_PS_MAX_THREADS_SHIFT : IVB_PS_MAX_THREADS_SHIFT;
 120
 121    /* BRW_NEW_PS_BINDING_TABLE */
 122    BEGIN_BATCH(2);
 123    OUT_BATCH(_3DSTATE_BINDING_TABLE_POINTERS_PS << 16 | (2 - 2));
 124    OUT_BATCH(brw->wm.bind_bo_offset);
 125    ADVANCE_BATCH();
 126
 127    /* CACHE_NEW_SAMPLER */
 128    BEGIN_BATCH(2);
 129    OUT_BATCH(_3DSTATE_SAMPLER_STATE_POINTERS_PS << 16 | (2 - 2));
 130    OUT_BATCH(brw->sampler.offset);
 131    ADVANCE_BATCH();
 132
 133    /* CACHE_NEW_WM_PROG */
 134    if (brw->wm.prog_data->nr_params == 0) {
 135       /* Disable the push constant buffers. */
 136       BEGIN_BATCH(7);
 137       OUT_BATCH(_3DSTATE_CONSTANT_PS << 16 | (7 - 2));
 138       OUT_BATCH(0);
 139       OUT_BATCH(0);
 140       OUT_BATCH(0);
 141       OUT_BATCH(0);
 142       OUT_BATCH(0);
 143       OUT_BATCH(0);
 144       ADVANCE_BATCH();
 145    } else {
 146       BEGIN_BATCH(7);
 147       OUT_BATCH(_3DSTATE_CONSTANT_PS << 16 | (7 - 2));
 148
 149       OUT_BATCH(ALIGN(brw->wm.prog_data->nr_params,
 150                       brw->wm.prog_data->dispatch_width) / 8);
 151       OUT_BATCH(0);
 152       /* Pointer to the WM constant buffer.  Covered by the set of
 153        * state flags from gen6_upload_wm_push_constants.
 154        */
 155       OUT_BATCH(brw->wm.push_const_offset);
 156       OUT_BATCH(0);
 157       OUT_BATCH(0);
 158       OUT_BATCH(0);
 159       ADVANCE_BATCH();
 160    }
 161
 162    dw2 = dw4 = dw5 = 0;
 163
 164    /* CACHE_NEW_SAMPLER */
 165    dw2 |= (ALIGN(brw->sampler.count, 4) / 4) << GEN7_PS_SAMPLER_COUNT_SHIFT;
 166
 167    /* Use ALT floating point mode for ARB fragment programs, because they
 168     * require 0^0 == 1.  Even though _CurrentFragmentProgram is used for
 169     * rendering, CurrentFragmentProgram is used for this check to
 170     * differentiate between the GLSL and non-GLSL cases.
 171     */
 172    if (intel->ctx.Shader.CurrentFragmentProgram == NULL)
 173       dw2 |= GEN7_PS_FLOATING_POINT_MODE_ALT;
 174
 175    if (intel->is_haswell)
 176       dw4 |= SET_FIELD(1, HSW_PS_SAMPLE_MASK); /* 1 sample for now */
 177
 178    dw4 |= (brw->max_wm_threads - 1) << max_threads_shift;
 179
 180    /* CACHE_NEW_WM_PROG */
 181    if (brw->wm.prog_data->nr_params > 0)
 182       dw4 |= GEN7_PS_PUSH_CONSTANT_ENABLE;
 183
 184    /* CACHE_NEW_WM_PROG | _NEW_COLOR
 185     *
 186     * The hardware wedges if you have this bit set but don't turn on any dual
 187     * source blend factors.
 188     */
 189    if (brw->wm.prog_data->dual_src_blend &&
 190        (ctx->Color.BlendEnabled & 1) &&
 191        ctx->Color.Blend[0]._UsesDualSrc) {
 192       dw4 |= GEN7_PS_DUAL_SOURCE_BLEND_ENABLE;
 193    }
 194
 195    /* BRW_NEW_FRAGMENT_PROGRAM */
 196    if (brw->fragment_program->Base.InputsRead != 0)
 197       dw4 |= GEN7_PS_ATTRIBUTE_ENABLE;
 198
 199    dw4 |= GEN7_PS_8_DISPATCH_ENABLE;
 200    if (brw->wm.prog_data->prog_offset_16)
 201       dw4 |= GEN7_PS_16_DISPATCH_ENABLE;
 202
 203    dw5 |= (brw->wm.prog_data->first_curbe_grf <<
 204            GEN7_PS_DISPATCH_START_GRF_SHIFT_0);
 205    dw5 |= (brw->wm.prog_data->first_curbe_grf_16 <<
 206            GEN7_PS_DISPATCH_START_GRF_SHIFT_2);
 207
 208    BEGIN_BATCH(8);
 209    OUT_BATCH(_3DSTATE_PS << 16 | (8 - 2));
 210    OUT_BATCH(brw->wm.prog_offset);
 211    OUT_BATCH(dw2);
 212    if (brw->wm.prog_data->total_scratch) {
 213       OUT_RELOC(brw->wm.scratch_bo,
 214                 I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
 215                 ffs(brw->wm.prog_data->total_scratch) - 11);
 216    } else {
 217       OUT_BATCH(0);
 218    }
 219    OUT_BATCH(dw4);
 220    OUT_BATCH(dw5);
 221    OUT_BATCH(0); /* kernel 1 pointer */
 222    OUT_BATCH(brw->wm.prog_offset + brw->wm.prog_data->prog_offset_16);
 223    ADVANCE_BATCH();
 224 }
 225
 226 const struct brw_tracked_state gen7_ps_state = {
 227    .dirty = {
 228       .mesa  = (_NEW_PROGRAM_CONSTANTS |
 229                 _NEW_COLOR),
 230       .brw   = (BRW_NEW_FRAGMENT_PROGRAM |
 231                 BRW_NEW_PS_BINDING_TABLE |
 232                 BRW_NEW_BATCH),
 233       .cache = (CACHE_NEW_SAMPLER |
 234                 CACHE_NEW_WM_PROG)
 235    },
 236    .emit = upload_ps_state,
 237 };