2 * Copyright © 2011 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 #include "brw_context.h"
26 #include "brw_state.h"
27 #include "brw_defines.h"
30 #include "program/program.h"
31 #include "program/prog_parameter.h"
32 #include "program/prog_statevars.h"
33 #include "intel_batchbuffer.h"
36 upload_wm_state(struct brw_context
*brw
)
38 struct gl_context
*ctx
= &brw
->ctx
;
39 const struct brw_fragment_program
*fp
=
40 brw_fragment_program_const(brw
->fragment_program
);
41 bool writes_depth
= false;
45 bool multisampled_fbo
= ctx
->DrawBuffer
->Visual
.samples
> 1;
48 dw1
|= GEN7_WM_STATISTICS_ENABLE
;
49 dw1
|= GEN7_WM_LINE_AA_WIDTH_1_0
;
50 dw1
|= GEN7_WM_LINE_END_CAP_AA_WIDTH_0_5
;
53 if (ctx
->Line
.StippleFlag
)
54 dw1
|= GEN7_WM_LINE_STIPPLE_ENABLE
;
57 if (ctx
->Polygon
.StippleFlag
)
58 dw1
|= GEN7_WM_POLYGON_STIPPLE_ENABLE
;
60 /* BRW_NEW_FRAGMENT_PROGRAM */
61 if (fp
->program
.Base
.InputsRead
& VARYING_BIT_POS
)
62 dw1
|= GEN7_WM_USES_SOURCE_DEPTH
| GEN7_WM_USES_SOURCE_W
;
63 if (fp
->program
.Base
.OutputsWritten
& BITFIELD64_BIT(FRAG_RESULT_DEPTH
)) {
64 writes_depth
= fp
->program
.FragDepthLayout
!= FRAG_DEPTH_LAYOUT_UNCHANGED
;
66 switch (fp
->program
.FragDepthLayout
) {
67 case FRAG_DEPTH_LAYOUT_NONE
:
68 case FRAG_DEPTH_LAYOUT_ANY
:
69 dw1
|= GEN7_WM_PSCDEPTH_ON
;
71 case FRAG_DEPTH_LAYOUT_GREATER
:
72 dw1
|= GEN7_WM_PSCDEPTH_ON_GE
;
74 case FRAG_DEPTH_LAYOUT_LESS
:
75 dw1
|= GEN7_WM_PSCDEPTH_ON_LE
;
77 case FRAG_DEPTH_LAYOUT_UNCHANGED
:
81 /* CACHE_NEW_WM_PROG */
82 dw1
|= brw
->wm
.prog_data
->barycentric_interp_modes
<<
83 GEN7_WM_BARYCENTRIC_INTERPOLATION_MODE_SHIFT
;
85 /* _NEW_COLOR, _NEW_MULTISAMPLE */
86 /* Enable if the pixel shader kernel generates and outputs oMask.
88 if (fp
->program
.UsesKill
|| ctx
->Color
.AlphaEnabled
||
89 ctx
->Multisample
.SampleAlphaToCoverage
||
90 brw
->wm
.prog_data
->uses_omask
) {
91 dw1
|= GEN7_WM_KILL_ENABLE
;
95 if (brw_color_buffer_write_enabled(brw
) || writes_depth
||
96 dw1
& GEN7_WM_KILL_ENABLE
) {
97 dw1
|= GEN7_WM_DISPATCH_ENABLE
;
99 if (multisampled_fbo
) {
100 /* _NEW_MULTISAMPLE */
101 if (ctx
->Multisample
.Enabled
)
102 dw1
|= GEN7_WM_MSRAST_ON_PATTERN
;
104 dw1
|= GEN7_WM_MSRAST_OFF_PIXEL
;
106 if (_mesa_get_min_invocations_per_fragment(ctx
, brw
->fragment_program
, false) > 1)
107 dw2
|= GEN7_WM_MSDISPMODE_PERSAMPLE
;
109 dw2
|= GEN7_WM_MSDISPMODE_PERPIXEL
;
111 dw1
|= GEN7_WM_MSRAST_OFF_PIXEL
;
112 dw2
|= GEN7_WM_MSDISPMODE_PERSAMPLE
;
115 if (fp
->program
.Base
.SystemValuesRead
& SYSTEM_BIT_SAMPLE_MASK_IN
) {
116 dw1
|= GEN7_WM_USES_INPUT_COVERAGE_MASK
;
120 OUT_BATCH(_3DSTATE_WM
<< 16 | (3 - 2));
126 const struct brw_tracked_state gen7_wm_state
= {
128 .mesa
= (_NEW_LINE
| _NEW_POLYGON
|
129 _NEW_COLOR
| _NEW_BUFFERS
|
131 .brw
= (BRW_NEW_FRAGMENT_PROGRAM
|
133 .cache
= CACHE_NEW_WM_PROG
,
135 .emit
= upload_wm_state
,
139 upload_ps_state(struct brw_context
*brw
)
141 struct gl_context
*ctx
= &brw
->ctx
;
142 uint32_t dw2
, dw4
, dw5
;
143 const int max_threads_shift
= brw
->is_haswell
?
144 HSW_PS_MAX_THREADS_SHIFT
: IVB_PS_MAX_THREADS_SHIFT
;
146 /* CACHE_NEW_SAMPLER */
148 OUT_BATCH(_3DSTATE_SAMPLER_STATE_POINTERS_PS
<< 16 | (2 - 2));
149 OUT_BATCH(brw
->wm
.base
.sampler_offset
);
152 /* CACHE_NEW_WM_PROG */
153 gen7_upload_constant_state(brw
, &brw
->wm
.base
, true, _3DSTATE_CONSTANT_PS
);
157 /* CACHE_NEW_SAMPLER */
159 (ALIGN(brw
->wm
.base
.sampler_count
, 4) / 4) << GEN7_PS_SAMPLER_COUNT_SHIFT
;
161 /* CACHE_NEW_WM_PROG */
162 dw2
|= ((brw
->wm
.prog_data
->base
.binding_table
.size_bytes
/ 4) <<
163 GEN7_PS_BINDING_TABLE_ENTRY_COUNT_SHIFT
);
165 /* Use ALT floating point mode for ARB fragment programs, because they
166 * require 0^0 == 1. Even though _CurrentFragmentProgram is used for
167 * rendering, CurrentProgram[MESA_SHADER_FRAGMENT] is used for this check
168 * to differentiate between the GLSL and non-GLSL cases.
170 /* BRW_NEW_FRAGMENT_PROGRAM */
171 if (ctx
->Shader
.CurrentProgram
[MESA_SHADER_FRAGMENT
] == NULL
)
172 dw2
|= GEN7_PS_FLOATING_POINT_MODE_ALT
;
174 /* Haswell requires the sample mask to be set in this packet as well as
175 * in 3DSTATE_SAMPLE_MASK; the values should match. */
176 /* _NEW_BUFFERS, _NEW_MULTISAMPLE */
178 dw4
|= SET_FIELD(gen6_determine_sample_mask(brw
), HSW_PS_SAMPLE_MASK
);
180 dw4
|= (brw
->max_wm_threads
- 1) << max_threads_shift
;
182 /* CACHE_NEW_WM_PROG */
183 if (brw
->wm
.prog_data
->base
.nr_params
> 0)
184 dw4
|= GEN7_PS_PUSH_CONSTANT_ENABLE
;
186 /* From the IVB PRM, volume 2 part 1, page 287:
187 * "This bit is inserted in the PS payload header and made available to
188 * the DataPort (either via the message header or via header bypass) to
189 * indicate that oMask data (one or two phases) is included in Render
190 * Target Write messages. If present, the oMask data is used to mask off
193 if (brw
->wm
.prog_data
->uses_omask
)
194 dw4
|= GEN7_PS_OMASK_TO_RENDER_TARGET
;
196 /* From the IVB PRM, volume 2 part 1, page 287:
197 * "If the PS kernel does not need the Position XY Offsets to
198 * compute a Position Value, then this field should be programmed
199 * to POSOFFSET_NONE."
200 * "SW Recommendation: If the PS kernel needs the Position Offsets
201 * to compute a Position XY value, this field should match Position
202 * ZW Interpolation Mode to ensure a consistent position.xyzw
204 * We only require XY sample offsets. So, this recommendation doesn't
205 * look useful at the moment. We might need this in future.
207 if (brw
->wm
.prog_data
->uses_pos_offset
)
208 dw4
|= GEN7_PS_POSOFFSET_SAMPLE
;
210 dw4
|= GEN7_PS_POSOFFSET_NONE
;
212 /* CACHE_NEW_WM_PROG | _NEW_COLOR
214 * The hardware wedges if you have this bit set but don't turn on any dual
215 * source blend factors.
217 if (brw
->wm
.prog_data
->dual_src_blend
&&
218 (ctx
->Color
.BlendEnabled
& 1) &&
219 ctx
->Color
.Blend
[0]._UsesDualSrc
) {
220 dw4
|= GEN7_PS_DUAL_SOURCE_BLEND_ENABLE
;
223 /* CACHE_NEW_WM_PROG */
224 if (brw
->wm
.prog_data
->num_varying_inputs
!= 0)
225 dw4
|= GEN7_PS_ATTRIBUTE_ENABLE
;
227 /* In case of non 1x per sample shading, only one of SIMD8 and SIMD16
228 * should be enabled. We do 'SIMD16 only' dispatch if a SIMD16 shader
229 * is successfully compiled. In majority of the cases that bring us
230 * better performance than 'SIMD8 only' dispatch.
232 int min_inv_per_frag
=
233 _mesa_get_min_invocations_per_fragment(ctx
, brw
->fragment_program
, false);
234 assert(min_inv_per_frag
>= 1);
236 if (brw
->wm
.prog_data
->prog_offset_16
) {
237 dw4
|= GEN7_PS_16_DISPATCH_ENABLE
;
238 if (min_inv_per_frag
== 1) {
239 dw4
|= GEN7_PS_8_DISPATCH_ENABLE
;
240 dw5
|= (brw
->wm
.prog_data
->first_curbe_grf
<<
241 GEN7_PS_DISPATCH_START_GRF_SHIFT_0
);
242 dw5
|= (brw
->wm
.prog_data
->first_curbe_grf_16
<<
243 GEN7_PS_DISPATCH_START_GRF_SHIFT_2
);
245 dw5
|= (brw
->wm
.prog_data
->first_curbe_grf_16
<<
246 GEN7_PS_DISPATCH_START_GRF_SHIFT_0
);
249 dw4
|= GEN7_PS_8_DISPATCH_ENABLE
;
250 dw5
|= (brw
->wm
.prog_data
->first_curbe_grf
<<
251 GEN7_PS_DISPATCH_START_GRF_SHIFT_0
);
255 OUT_BATCH(_3DSTATE_PS
<< 16 | (8 - 2));
256 if (brw
->wm
.prog_data
->prog_offset_16
&& min_inv_per_frag
> 1)
257 OUT_BATCH(brw
->wm
.base
.prog_offset
+ brw
->wm
.prog_data
->prog_offset_16
);
259 OUT_BATCH(brw
->wm
.base
.prog_offset
);
261 if (brw
->wm
.prog_data
->total_scratch
) {
262 OUT_RELOC(brw
->wm
.base
.scratch_bo
,
263 I915_GEM_DOMAIN_RENDER
, I915_GEM_DOMAIN_RENDER
,
264 ffs(brw
->wm
.prog_data
->total_scratch
) - 11);
270 OUT_BATCH(0); /* kernel 1 pointer */
271 OUT_BATCH(brw
->wm
.base
.prog_offset
+ brw
->wm
.prog_data
->prog_offset_16
);
275 const struct brw_tracked_state gen7_ps_state
= {
277 .mesa
= (_NEW_PROGRAM_CONSTANTS
|
281 .brw
= (BRW_NEW_FRAGMENT_PROGRAM
|
282 BRW_NEW_PS_BINDING_TABLE
|
284 BRW_NEW_PUSH_CONSTANT_ALLOCATION
),
285 .cache
= (CACHE_NEW_SAMPLER
|
288 .emit
= upload_ps_state
,