src/mesa/drivers/dri/i965/gen7_wm_state.c

   1 /*
   2  * Copyright © 2011 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include <stdbool.h>
  25 #include "brw_context.h"
  26 #include "brw_state.h"
  27 #include "brw_defines.h"
  28 #include "brw_util.h"
  29 #include "brw_wm.h"
  30 #include "program/program.h"
  31 #include "program/prog_parameter.h"
  32 #include "program/prog_statevars.h"
  33 #include "main/framebuffer.h"
  34 #include "intel_batchbuffer.h"
  35
  36 static void
  37 upload_wm_state(struct brw_context *brw)
  38 {
  39    struct gl_context *ctx = &brw->ctx;
  40    /* BRW_NEW_FRAGMENT_PROGRAM */
  41    const struct brw_fragment_program *fp =
  42       brw_fragment_program_const(brw->fragment_program);
  43    /* BRW_NEW_FS_PROG_DATA */
  44    const struct brw_wm_prog_data *prog_data = brw->wm.prog_data;
  45    bool writes_depth = prog_data->computed_depth_mode != BRW_PSCDEPTH_OFF;
  46    uint32_t dw1, dw2;
  47
  48    /* _NEW_BUFFERS */
  49    const bool multisampled_fbo = _mesa_geometric_samples(ctx->DrawBuffer) > 1;
  50
  51    dw1 = dw2 = 0;
  52    dw1 |= GEN7_WM_STATISTICS_ENABLE;
  53    dw1 |= GEN7_WM_LINE_AA_WIDTH_1_0;
  54    dw1 |= GEN7_WM_LINE_END_CAP_AA_WIDTH_0_5;
  55
  56    /* _NEW_LINE */
  57    if (ctx->Line.StippleFlag)
  58       dw1 |= GEN7_WM_LINE_STIPPLE_ENABLE;
  59
  60    /* _NEW_POLYGON */
  61    if (ctx->Polygon.StippleFlag)
  62       dw1 |= GEN7_WM_POLYGON_STIPPLE_ENABLE;
  63
  64    if (fp->program.Base.InputsRead & VARYING_BIT_POS)
  65       dw1 |= GEN7_WM_USES_SOURCE_DEPTH | GEN7_WM_USES_SOURCE_W;
  66
  67    dw1 |= prog_data->computed_depth_mode << GEN7_WM_COMPUTED_DEPTH_MODE_SHIFT;
  68    dw1 |= prog_data->barycentric_interp_modes <<
  69       GEN7_WM_BARYCENTRIC_INTERPOLATION_MODE_SHIFT;
  70
  71    /* _NEW_COLOR, _NEW_MULTISAMPLE */
  72    /* Enable if the pixel shader kernel generates and outputs oMask.
  73     */
  74    if (prog_data->uses_kill || ctx->Color.AlphaEnabled ||
  75        ctx->Multisample.SampleAlphaToCoverage ||
  76        prog_data->uses_omask) {
  77       dw1 |= GEN7_WM_KILL_ENABLE;
  78    }
  79
  80    if (_mesa_active_fragment_shader_has_atomic_ops(&brw->ctx)) {
  81       dw1 |= GEN7_WM_DISPATCH_ENABLE;
  82    }
  83
  84    /* _NEW_BUFFERS | _NEW_COLOR */
  85    if (brw_color_buffer_write_enabled(brw) || writes_depth ||
  86        dw1 & GEN7_WM_KILL_ENABLE) {
  87       dw1 |= GEN7_WM_DISPATCH_ENABLE;
  88    }
  89    if (multisampled_fbo) {
  90       /* _NEW_MULTISAMPLE */
  91       if (ctx->Multisample.Enabled)
  92          dw1 |= GEN7_WM_MSRAST_ON_PATTERN;
  93       else
  94          dw1 |= GEN7_WM_MSRAST_OFF_PIXEL;
  95
  96       if (_mesa_get_min_invocations_per_fragment(ctx, brw->fragment_program, false) > 1)
  97          dw2 |= GEN7_WM_MSDISPMODE_PERSAMPLE;
  98       else
  99          dw2 |= GEN7_WM_MSDISPMODE_PERPIXEL;
 100    } else {
 101       dw1 |= GEN7_WM_MSRAST_OFF_PIXEL;
 102       dw2 |= GEN7_WM_MSDISPMODE_PERSAMPLE;
 103    }
 104
 105    if (fp->program.Base.SystemValuesRead & SYSTEM_BIT_SAMPLE_MASK_IN) {
 106       dw1 |= GEN7_WM_USES_INPUT_COVERAGE_MASK;
 107    }
 108
 109    BEGIN_BATCH(3);
 110    OUT_BATCH(_3DSTATE_WM << 16 | (3 - 2));
 111    OUT_BATCH(dw1);
 112    OUT_BATCH(dw2);
 113    ADVANCE_BATCH();
 114 }
 115
 116 const struct brw_tracked_state gen7_wm_state = {
 117    .dirty = {
 118       .mesa  = _NEW_BUFFERS |
 119                _NEW_COLOR |
 120                _NEW_LINE |
 121                _NEW_MULTISAMPLE |
 122                _NEW_POLYGON,
 123       .brw   = BRW_NEW_BATCH |
 124                BRW_NEW_FRAGMENT_PROGRAM |
 125                BRW_NEW_FS_PROG_DATA,
 126    },
 127    .emit = upload_wm_state,
 128 };
 129
 130 void
 131 gen7_upload_ps_state(struct brw_context *brw,
 132                      const struct gl_fragment_program *fp,
 133                      const struct brw_stage_state *stage_state,
 134                      const struct brw_wm_prog_data *prog_data,
 135                      bool enable_dual_src_blend, unsigned sample_mask,
 136                      unsigned fast_clear_op)
 137 {
 138    struct gl_context *ctx = &brw->ctx;
 139    uint32_t dw2, dw4, dw5, ksp0, ksp2;
 140    const int max_threads_shift = brw->is_haswell ?
 141       HSW_PS_MAX_THREADS_SHIFT : IVB_PS_MAX_THREADS_SHIFT;
 142
 143    dw2 = dw4 = dw5 = ksp2 = 0;
 144
 145    const unsigned sampler_count =
 146       DIV_ROUND_UP(CLAMP(stage_state->sampler_count, 0, 16), 4);
 147    dw2 |= SET_FIELD(sampler_count, GEN7_PS_SAMPLER_COUNT);
 148
 149    dw2 |= ((prog_data->base.binding_table.size_bytes / 4) <<
 150            GEN7_PS_BINDING_TABLE_ENTRY_COUNT_SHIFT);
 151
 152    if (prog_data->base.use_alt_mode)
 153       dw2 |= GEN7_PS_FLOATING_POINT_MODE_ALT;
 154
 155    /* Haswell requires the sample mask to be set in this packet as well as
 156     * in 3DSTATE_SAMPLE_MASK; the values should match. */
 157    /* _NEW_BUFFERS, _NEW_MULTISAMPLE */
 158    if (brw->is_haswell)
 159       dw4 |= SET_FIELD(sample_mask, HSW_PS_SAMPLE_MASK);
 160
 161    dw4 |= (brw->max_wm_threads - 1) << max_threads_shift;
 162
 163    if (prog_data->base.nr_params > 0)
 164       dw4 |= GEN7_PS_PUSH_CONSTANT_ENABLE;
 165
 166    /* From the IVB PRM, volume 2 part 1, page 287:
 167     * "This bit is inserted in the PS payload header and made available to
 168     * the DataPort (either via the message header or via header bypass) to
 169     * indicate that oMask data (one or two phases) is included in Render
 170     * Target Write messages. If present, the oMask data is used to mask off
 171     * samples."
 172     */
 173    if (prog_data->uses_omask)
 174       dw4 |= GEN7_PS_OMASK_TO_RENDER_TARGET;
 175
 176    /* From the IVB PRM, volume 2 part 1, page 287:
 177     * "If the PS kernel does not need the Position XY Offsets to
 178     * compute a Position Value, then this field should be programmed
 179     * to POSOFFSET_NONE."
 180     * "SW Recommendation: If the PS kernel needs the Position Offsets
 181     * to compute a Position XY value, this field should match Position
 182     * ZW Interpolation Mode to ensure a consistent position.xyzw
 183     * computation."
 184     * We only require XY sample offsets. So, this recommendation doesn't
 185     * look useful at the moment. We might need this in future.
 186     */
 187    if (prog_data->uses_pos_offset)
 188       dw4 |= GEN7_PS_POSOFFSET_SAMPLE;
 189    else
 190       dw4 |= GEN7_PS_POSOFFSET_NONE;
 191
 192    /* The hardware wedges if you have this bit set but don't turn on any dual
 193     * source blend factors.
 194     */
 195    if (enable_dual_src_blend)
 196       dw4 |= GEN7_PS_DUAL_SOURCE_BLEND_ENABLE;
 197
 198    /* BRW_NEW_FS_PROG_DATA */
 199    if (prog_data->num_varying_inputs != 0)
 200       dw4 |= GEN7_PS_ATTRIBUTE_ENABLE;
 201
 202    /* In case of non 1x per sample shading, only one of SIMD8 and SIMD16
 203     * should be enabled. We do 'SIMD16 only' dispatch if a SIMD16 shader
 204     * is successfully compiled. In majority of the cases that bring us
 205     * better performance than 'SIMD8 only' dispatch.
 206     */
 207    int min_inv_per_frag =
 208       _mesa_get_min_invocations_per_fragment(ctx, fp, false);
 209    assert(min_inv_per_frag >= 1);
 210
 211    if (prog_data->prog_offset_16 || prog_data->no_8) {
 212       dw4 |= GEN7_PS_16_DISPATCH_ENABLE;
 213       if (!prog_data->no_8 && min_inv_per_frag == 1) {
 214          dw4 |= GEN7_PS_8_DISPATCH_ENABLE;
 215          dw5 |= (prog_data->base.dispatch_grf_start_reg <<
 216                  GEN7_PS_DISPATCH_START_GRF_SHIFT_0);
 217          dw5 |= (prog_data->dispatch_grf_start_reg_16 <<
 218                  GEN7_PS_DISPATCH_START_GRF_SHIFT_2);
 219          ksp0 = stage_state->prog_offset;
 220          ksp2 = stage_state->prog_offset + prog_data->prog_offset_16;
 221       } else {
 222          dw5 |= (prog_data->dispatch_grf_start_reg_16 <<
 223                  GEN7_PS_DISPATCH_START_GRF_SHIFT_0);
 224          ksp0 = stage_state->prog_offset + prog_data->prog_offset_16;
 225       }
 226    }
 227    else {
 228       dw4 |= GEN7_PS_8_DISPATCH_ENABLE;
 229       dw5 |= (prog_data->base.dispatch_grf_start_reg <<
 230               GEN7_PS_DISPATCH_START_GRF_SHIFT_0);
 231       ksp0 = stage_state->prog_offset;
 232    }
 233
 234    dw4 |= fast_clear_op;
 235
 236    BEGIN_BATCH(8);
 237    OUT_BATCH(_3DSTATE_PS << 16 | (8 - 2));
 238    OUT_BATCH(ksp0);
 239    OUT_BATCH(dw2);
 240    if (prog_data->base.total_scratch) {
 241       OUT_RELOC(brw->wm.base.scratch_bo,
 242                 I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
 243                 ffs(prog_data->base.total_scratch) - 11);
 244    } else {
 245       OUT_BATCH(0);
 246    }
 247    OUT_BATCH(dw4);
 248    OUT_BATCH(dw5);
 249    OUT_BATCH(0); /* kernel 1 pointer */
 250    OUT_BATCH(ksp2);
 251    ADVANCE_BATCH();
 252 }
 253
 254 static void
 255 upload_ps_state(struct brw_context *brw)
 256 {
 257    /* BRW_NEW_FS_PROG_DATA */
 258    const struct brw_wm_prog_data *prog_data = brw->wm.prog_data;
 259    const struct gl_context *ctx = &brw->ctx;
 260    /* BRW_NEW_FS_PROG_DATA | _NEW_COLOR */
 261    const bool enable_dual_src_blend = prog_data->dual_src_blend &&
 262                                       (ctx->Color.BlendEnabled & 1) &&
 263                                       ctx->Color.Blend[0]._UsesDualSrc;
 264    /* _NEW_BUFFERS, _NEW_MULTISAMPLE */
 265    const unsigned sample_mask =
 266       brw->is_haswell ? gen6_determine_sample_mask(brw) : 0;
 267
 268    gen7_upload_ps_state(brw, brw->fragment_program, &brw->wm.base, prog_data,
 269                         enable_dual_src_blend, sample_mask,
 270                         brw->wm.fast_clear_op);
 271 }
 272
 273 const struct brw_tracked_state gen7_ps_state = {
 274    .dirty = {
 275       .mesa  = _NEW_BUFFERS |
 276                _NEW_COLOR |
 277                _NEW_MULTISAMPLE,
 278       .brw   = BRW_NEW_BATCH |
 279                BRW_NEW_FRAGMENT_PROGRAM |
 280                BRW_NEW_FS_PROG_DATA,
 281    },
 282    .emit = upload_ps_state,
 283 };