src/mesa/drivers/dri/i965/gen7_wm_state.c

   1 /*
   2  * Copyright © 2011 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include <stdbool.h>
  25 #include "brw_context.h"
  26 #include "brw_state.h"
  27 #include "brw_defines.h"
  28 #include "brw_util.h"
  29 #include "brw_wm.h"
  30 #include "program/program.h"
  31 #include "program/prog_parameter.h"
  32 #include "program/prog_statevars.h"
  33 #include "main/framebuffer.h"
  34 #include "intel_batchbuffer.h"
  35
  36 static void
  37 upload_wm_state(struct brw_context *brw)
  38 {
  39    struct gl_context *ctx = &brw->ctx;
  40    /* BRW_NEW_FRAGMENT_PROGRAM */
  41    const struct brw_fragment_program *fp =
  42       brw_fragment_program_const(brw->fragment_program);
  43    /* BRW_NEW_FS_PROG_DATA */
  44    const struct brw_wm_prog_data *prog_data = brw->wm.prog_data;
  45    bool writes_depth = prog_data->computed_depth_mode != BRW_PSCDEPTH_OFF;
  46    uint32_t dw1, dw2;
  47
  48    /* _NEW_BUFFERS */
  49    const bool multisampled_fbo = _mesa_geometric_samples(ctx->DrawBuffer) > 1;
  50
  51    dw1 = dw2 = 0;
  52    dw1 |= GEN7_WM_STATISTICS_ENABLE;
  53    dw1 |= GEN7_WM_LINE_AA_WIDTH_1_0;
  54    dw1 |= GEN7_WM_LINE_END_CAP_AA_WIDTH_0_5;
  55
  56    /* _NEW_LINE */
  57    if (ctx->Line.StippleFlag)
  58       dw1 |= GEN7_WM_LINE_STIPPLE_ENABLE;
  59
  60    /* _NEW_POLYGON */
  61    if (ctx->Polygon.StippleFlag)
  62       dw1 |= GEN7_WM_POLYGON_STIPPLE_ENABLE;
  63
  64    if (fp->program.Base.InputsRead & VARYING_BIT_POS)
  65       dw1 |= GEN7_WM_USES_SOURCE_DEPTH | GEN7_WM_USES_SOURCE_W;
  66
  67    dw1 |= prog_data->computed_depth_mode << GEN7_WM_COMPUTED_DEPTH_MODE_SHIFT;
  68    dw1 |= prog_data->barycentric_interp_modes <<
  69       GEN7_WM_BARYCENTRIC_INTERPOLATION_MODE_SHIFT;
  70
  71    /* _NEW_COLOR, _NEW_MULTISAMPLE */
  72    /* Enable if the pixel shader kernel generates and outputs oMask.
  73     */
  74    if (prog_data->uses_kill || ctx->Color.AlphaEnabled ||
  75        ctx->Multisample.SampleAlphaToCoverage ||
  76        prog_data->uses_omask) {
  77       dw1 |= GEN7_WM_KILL_ENABLE;
  78    }
  79
  80    if (_mesa_active_fragment_shader_has_atomic_ops(&brw->ctx)) {
  81       dw1 |= GEN7_WM_DISPATCH_ENABLE;
  82    }
  83
  84    /* _NEW_BUFFERS | _NEW_COLOR */
  85    if (brw_color_buffer_write_enabled(brw) || writes_depth ||
  86        prog_data->base.nr_image_params ||
  87        dw1 & GEN7_WM_KILL_ENABLE) {
  88       dw1 |= GEN7_WM_DISPATCH_ENABLE;
  89    }
  90    if (multisampled_fbo) {
  91       /* _NEW_MULTISAMPLE */
  92       if (ctx->Multisample.Enabled)
  93          dw1 |= GEN7_WM_MSRAST_ON_PATTERN;
  94       else
  95          dw1 |= GEN7_WM_MSRAST_OFF_PIXEL;
  96
  97       if (_mesa_get_min_invocations_per_fragment(ctx, brw->fragment_program, false) > 1)
  98          dw2 |= GEN7_WM_MSDISPMODE_PERSAMPLE;
  99       else
 100          dw2 |= GEN7_WM_MSDISPMODE_PERPIXEL;
 101    } else {
 102       dw1 |= GEN7_WM_MSRAST_OFF_PIXEL;
 103       dw2 |= GEN7_WM_MSDISPMODE_PERSAMPLE;
 104    }
 105
 106    if (fp->program.Base.SystemValuesRead & SYSTEM_BIT_SAMPLE_MASK_IN) {
 107       dw1 |= GEN7_WM_USES_INPUT_COVERAGE_MASK;
 108    }
 109
 110    /* BRW_NEW_FS_PROG_DATA */
 111    if (prog_data->early_fragment_tests)
 112       dw1 |= GEN7_WM_EARLY_DS_CONTROL_PREPS;
 113    else if (prog_data->base.nr_image_params)
 114       dw1 |= GEN7_WM_EARLY_DS_CONTROL_PSEXEC;
 115
 116    /* _NEW_BUFFERS | _NEW_COLOR */
 117    if (brw->is_haswell &&
 118        !(brw_color_buffer_write_enabled(brw) || writes_depth) &&
 119        prog_data->base.nr_image_params)
 120       dw2 |= HSW_WM_UAV_ONLY;
 121
 122    BEGIN_BATCH(3);
 123    OUT_BATCH(_3DSTATE_WM << 16 | (3 - 2));
 124    OUT_BATCH(dw1);
 125    OUT_BATCH(dw2);
 126    ADVANCE_BATCH();
 127 }
 128
 129 const struct brw_tracked_state gen7_wm_state = {
 130    .dirty = {
 131       .mesa  = _NEW_BUFFERS |
 132                _NEW_COLOR |
 133                _NEW_LINE |
 134                _NEW_MULTISAMPLE |
 135                _NEW_POLYGON,
 136       .brw   = BRW_NEW_BATCH |
 137                BRW_NEW_FRAGMENT_PROGRAM |
 138                BRW_NEW_FS_PROG_DATA,
 139    },
 140    .emit = upload_wm_state,
 141 };
 142
 143 static void
 144 gen7_upload_ps_state(struct brw_context *brw,
 145                      const struct gl_fragment_program *fp,
 146                      const struct brw_stage_state *stage_state,
 147                      const struct brw_wm_prog_data *prog_data,
 148                      bool enable_dual_src_blend, unsigned sample_mask,
 149                      unsigned fast_clear_op)
 150 {
 151    struct gl_context *ctx = &brw->ctx;
 152    uint32_t dw2, dw4, dw5, ksp0, ksp2;
 153    const int max_threads_shift = brw->is_haswell ?
 154       HSW_PS_MAX_THREADS_SHIFT : IVB_PS_MAX_THREADS_SHIFT;
 155
 156    dw2 = dw4 = dw5 = ksp2 = 0;
 157
 158    const unsigned sampler_count =
 159       DIV_ROUND_UP(CLAMP(stage_state->sampler_count, 0, 16), 4);
 160    dw2 |= SET_FIELD(sampler_count, GEN7_PS_SAMPLER_COUNT);
 161
 162    dw2 |= ((prog_data->base.binding_table.size_bytes / 4) <<
 163            GEN7_PS_BINDING_TABLE_ENTRY_COUNT_SHIFT);
 164
 165    if (prog_data->base.use_alt_mode)
 166       dw2 |= GEN7_PS_FLOATING_POINT_MODE_ALT;
 167
 168    /* Haswell requires the sample mask to be set in this packet as well as
 169     * in 3DSTATE_SAMPLE_MASK; the values should match. */
 170    /* _NEW_BUFFERS, _NEW_MULTISAMPLE */
 171    if (brw->is_haswell)
 172       dw4 |= SET_FIELD(sample_mask, HSW_PS_SAMPLE_MASK);
 173
 174    dw4 |= (brw->max_wm_threads - 1) << max_threads_shift;
 175
 176    if (prog_data->base.nr_params > 0)
 177       dw4 |= GEN7_PS_PUSH_CONSTANT_ENABLE;
 178
 179    /* From the IVB PRM, volume 2 part 1, page 287:
 180     * "This bit is inserted in the PS payload header and made available to
 181     * the DataPort (either via the message header or via header bypass) to
 182     * indicate that oMask data (one or two phases) is included in Render
 183     * Target Write messages. If present, the oMask data is used to mask off
 184     * samples."
 185     */
 186    if (prog_data->uses_omask)
 187       dw4 |= GEN7_PS_OMASK_TO_RENDER_TARGET;
 188
 189    /* From the IVB PRM, volume 2 part 1, page 287:
 190     * "If the PS kernel does not need the Position XY Offsets to
 191     * compute a Position Value, then this field should be programmed
 192     * to POSOFFSET_NONE."
 193     * "SW Recommendation: If the PS kernel needs the Position Offsets
 194     * to compute a Position XY value, this field should match Position
 195     * ZW Interpolation Mode to ensure a consistent position.xyzw
 196     * computation."
 197     * We only require XY sample offsets. So, this recommendation doesn't
 198     * look useful at the moment. We might need this in future.
 199     */
 200    if (prog_data->uses_pos_offset)
 201       dw4 |= GEN7_PS_POSOFFSET_SAMPLE;
 202    else
 203       dw4 |= GEN7_PS_POSOFFSET_NONE;
 204
 205    /* The hardware wedges if you have this bit set but don't turn on any dual
 206     * source blend factors.
 207     */
 208    if (enable_dual_src_blend)
 209       dw4 |= GEN7_PS_DUAL_SOURCE_BLEND_ENABLE;
 210
 211    /* BRW_NEW_FS_PROG_DATA */
 212    if (prog_data->num_varying_inputs != 0)
 213       dw4 |= GEN7_PS_ATTRIBUTE_ENABLE;
 214
 215    /* In case of non 1x per sample shading, only one of SIMD8 and SIMD16
 216     * should be enabled. We do 'SIMD16 only' dispatch if a SIMD16 shader
 217     * is successfully compiled. In majority of the cases that bring us
 218     * better performance than 'SIMD8 only' dispatch.
 219     */
 220    int min_inv_per_frag =
 221       _mesa_get_min_invocations_per_fragment(ctx, fp, false);
 222    assert(min_inv_per_frag >= 1);
 223
 224    if (brw->is_haswell && prog_data->base.nr_image_params)
 225       dw4 |= HSW_PS_UAV_ACCESS_ENABLE;
 226
 227    if (prog_data->prog_offset_16 || prog_data->no_8) {
 228       dw4 |= GEN7_PS_16_DISPATCH_ENABLE;
 229       if (!prog_data->no_8 && min_inv_per_frag == 1) {
 230          dw4 |= GEN7_PS_8_DISPATCH_ENABLE;
 231          dw5 |= (prog_data->base.dispatch_grf_start_reg <<
 232                  GEN7_PS_DISPATCH_START_GRF_SHIFT_0);
 233          dw5 |= (prog_data->dispatch_grf_start_reg_16 <<
 234                  GEN7_PS_DISPATCH_START_GRF_SHIFT_2);
 235          ksp0 = stage_state->prog_offset;
 236          ksp2 = stage_state->prog_offset + prog_data->prog_offset_16;
 237       } else {
 238          dw5 |= (prog_data->dispatch_grf_start_reg_16 <<
 239                  GEN7_PS_DISPATCH_START_GRF_SHIFT_0);
 240          ksp0 = stage_state->prog_offset + prog_data->prog_offset_16;
 241       }
 242    }
 243    else {
 244       dw4 |= GEN7_PS_8_DISPATCH_ENABLE;
 245       dw5 |= (prog_data->base.dispatch_grf_start_reg <<
 246               GEN7_PS_DISPATCH_START_GRF_SHIFT_0);
 247       ksp0 = stage_state->prog_offset;
 248    }
 249
 250    dw4 |= fast_clear_op;
 251
 252    BEGIN_BATCH(8);
 253    OUT_BATCH(_3DSTATE_PS << 16 | (8 - 2));
 254    OUT_BATCH(ksp0);
 255    OUT_BATCH(dw2);
 256    if (prog_data->base.total_scratch) {
 257       OUT_RELOC(brw->wm.base.scratch_bo,
 258                 I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
 259                 ffs(prog_data->base.total_scratch) - 11);
 260    } else {
 261       OUT_BATCH(0);
 262    }
 263    OUT_BATCH(dw4);
 264    OUT_BATCH(dw5);
 265    OUT_BATCH(0); /* kernel 1 pointer */
 266    OUT_BATCH(ksp2);
 267    ADVANCE_BATCH();
 268 }
 269
 270 static void
 271 upload_ps_state(struct brw_context *brw)
 272 {
 273    /* BRW_NEW_FS_PROG_DATA */
 274    const struct brw_wm_prog_data *prog_data = brw->wm.prog_data;
 275    const struct gl_context *ctx = &brw->ctx;
 276    /* BRW_NEW_FS_PROG_DATA | _NEW_COLOR */
 277    const bool enable_dual_src_blend = prog_data->dual_src_blend &&
 278                                       (ctx->Color.BlendEnabled & 1) &&
 279                                       ctx->Color.Blend[0]._UsesDualSrc;
 280    /* _NEW_BUFFERS, _NEW_MULTISAMPLE */
 281    const unsigned sample_mask =
 282       brw->is_haswell ? gen6_determine_sample_mask(brw) : 0;
 283
 284    gen7_upload_ps_state(brw, brw->fragment_program, &brw->wm.base, prog_data,
 285                         enable_dual_src_blend, sample_mask,
 286                         brw->wm.fast_clear_op);
 287 }
 288
 289 const struct brw_tracked_state gen7_ps_state = {
 290    .dirty = {
 291       .mesa  = _NEW_BUFFERS |
 292                _NEW_COLOR |
 293                _NEW_MULTISAMPLE,
 294       .brw   = BRW_NEW_BATCH |
 295                BRW_NEW_FRAGMENT_PROGRAM |
 296                BRW_NEW_FS_PROG_DATA,
 297    },
 298    .emit = upload_ps_state,
 299 };