2 * Copyright © 2011 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 #include "brw_context.h"
26 #include "brw_state.h"
27 #include "brw_defines.h"
30 #include "program/prog_parameter.h"
31 #include "program/prog_statevars.h"
32 #include "intel_batchbuffer.h"
35 upload_wm_state(struct brw_context
*brw
)
37 struct intel_context
*intel
= &brw
->intel
;
38 struct gl_context
*ctx
= &intel
->ctx
;
39 const struct brw_fragment_program
*fp
=
40 brw_fragment_program_const(brw
->fragment_program
);
41 bool writes_depth
= false;
45 bool flat_shade
= (ctx
->Light
.ShadeModel
== GL_FLAT
);
48 dw1
|= GEN7_WM_STATISTICS_ENABLE
;
49 dw1
|= GEN7_WM_LINE_AA_WIDTH_1_0
;
50 dw1
|= GEN7_WM_LINE_END_CAP_AA_WIDTH_0_5
;
52 switch (brw
->hiz
.op
) {
55 case BRW_HIZ_OP_DEPTH_CLEAR
:
56 dw1
|= GEN7_WM_DEPTH_CLEAR
;
58 case BRW_HIZ_OP_DEPTH_RESOLVE
:
59 dw1
|= GEN7_WM_DEPTH_RESOLVE
;
61 case BRW_HIZ_OP_HIZ_RESOLVE
:
62 dw1
|= GEN7_WM_HIERARCHICAL_DEPTH_RESOLVE
;
70 if (ctx
->Line
.StippleFlag
)
71 dw1
|= GEN7_WM_LINE_STIPPLE_ENABLE
;
74 if (ctx
->Polygon
.StippleFlag
)
75 dw1
|= GEN7_WM_POLYGON_STIPPLE_ENABLE
;
77 /* BRW_NEW_FRAGMENT_PROGRAM */
78 if (fp
->program
.Base
.InputsRead
& FRAG_BIT_WPOS
)
79 dw1
|= GEN7_WM_USES_SOURCE_DEPTH
| GEN7_WM_USES_SOURCE_W
;
80 if (fp
->program
.Base
.OutputsWritten
& BITFIELD64_BIT(FRAG_RESULT_DEPTH
)) {
82 dw1
|= GEN7_WM_PSCDEPTH_ON
;
84 dw1
|= brw_compute_barycentric_interp_modes(flat_shade
, &fp
->program
) <<
85 GEN7_WM_BARYCENTRIC_INTERPOLATION_MODE_SHIFT
;
88 if (fp
->program
.UsesKill
|| ctx
->Color
.AlphaEnabled
)
89 dw1
|= GEN7_WM_KILL_ENABLE
;
92 if (brw_color_buffer_write_enabled(brw
) || writes_depth
||
93 dw1
& GEN7_WM_KILL_ENABLE
) {
94 dw1
|= GEN7_WM_DISPATCH_ENABLE
;
98 OUT_BATCH(_3DSTATE_WM
<< 16 | (3 - 2));
104 const struct brw_tracked_state gen7_wm_state
= {
106 .mesa
= (_NEW_LINE
| _NEW_LIGHT
| _NEW_POLYGON
|
107 _NEW_COLOR
| _NEW_BUFFERS
),
108 .brw
= (BRW_NEW_FRAGMENT_PROGRAM
|
113 .emit
= upload_wm_state
,
117 upload_ps_state(struct brw_context
*brw
)
119 struct intel_context
*intel
= &brw
->intel
;
120 uint32_t dw2
, dw4
, dw5
;
122 /* BRW_NEW_PS_BINDING_TABLE */
124 OUT_BATCH(_3DSTATE_BINDING_TABLE_POINTERS_PS
<< 16 | (2 - 2));
125 OUT_BATCH(brw
->bind
.bo_offset
);
128 /* CACHE_NEW_SAMPLER */
130 OUT_BATCH(_3DSTATE_SAMPLER_STATE_POINTERS_PS
<< 16 | (2 - 2));
131 OUT_BATCH(brw
->sampler
.offset
);
134 /* CACHE_NEW_WM_PROG */
135 if (brw
->wm
.prog_data
->nr_params
== 0) {
136 /* Disable the push constant buffers. */
138 OUT_BATCH(_3DSTATE_CONSTANT_PS
<< 16 | (7 - 2));
148 OUT_BATCH(_3DSTATE_CONSTANT_PS
<< 16 | (7 - 2));
150 OUT_BATCH(ALIGN(brw
->wm
.prog_data
->nr_params
,
151 brw
->wm
.prog_data
->dispatch_width
) / 8);
153 /* Pointer to the WM constant buffer. Covered by the set of
154 * state flags from gen6_upload_wm_push_constants.
156 OUT_BATCH(brw
->wm
.push_const_offset
);
165 /* CACHE_NEW_SAMPLER */
166 dw2
|= (ALIGN(brw
->sampler
.count
, 4) / 4) << GEN7_PS_SAMPLER_COUNT_SHIFT
;
168 /* Use ALT floating point mode for ARB fragment programs, because they
169 * require 0^0 == 1. Even though _CurrentFragmentProgram is used for
170 * rendering, CurrentFragmentProgram is used for this check to
171 * differentiate between the GLSL and non-GLSL cases.
173 if (intel
->ctx
.Shader
.CurrentFragmentProgram
== NULL
)
174 dw2
|= GEN7_PS_FLOATING_POINT_MODE_ALT
;
176 dw4
|= (brw
->max_wm_threads
- 1) << GEN7_PS_MAX_THREADS_SHIFT
;
178 /* CACHE_NEW_WM_PROG */
179 if (brw
->wm
.prog_data
->nr_params
> 0)
180 dw4
|= GEN7_PS_PUSH_CONSTANT_ENABLE
;
182 /* BRW_NEW_FRAGMENT_PROGRAM */
183 if (brw
->fragment_program
->Base
.InputsRead
!= 0)
184 dw4
|= GEN7_PS_ATTRIBUTE_ENABLE
;
186 if (brw
->wm
.prog_data
->dispatch_width
== 8) {
187 dw4
|= GEN7_PS_8_DISPATCH_ENABLE
;
188 if (brw
->wm
.prog_data
->prog_offset_16
)
189 dw4
|= GEN7_PS_16_DISPATCH_ENABLE
;
191 dw4
|= GEN7_PS_16_DISPATCH_ENABLE
;
194 dw5
|= (brw
->wm
.prog_data
->first_curbe_grf
<<
195 GEN7_PS_DISPATCH_START_GRF_SHIFT_0
);
196 dw5
|= (brw
->wm
.prog_data
->first_curbe_grf_16
<<
197 GEN7_PS_DISPATCH_START_GRF_SHIFT_2
);
200 OUT_BATCH(_3DSTATE_PS
<< 16 | (8 - 2));
201 OUT_BATCH(brw
->wm
.prog_offset
);
203 if (brw
->wm
.prog_data
->total_scratch
) {
204 OUT_RELOC(brw
->wm
.scratch_bo
,
205 I915_GEM_DOMAIN_RENDER
, I915_GEM_DOMAIN_RENDER
,
206 ffs(brw
->wm
.prog_data
->total_scratch
) - 11);
212 OUT_BATCH(0); /* kernel 1 pointer */
213 OUT_BATCH(brw
->wm
.prog_offset
+ brw
->wm
.prog_data
->prog_offset_16
);
217 const struct brw_tracked_state gen7_ps_state
= {
219 .mesa
= _NEW_PROGRAM_CONSTANTS
,
220 .brw
= (BRW_NEW_FRAGMENT_PROGRAM
|
221 BRW_NEW_PS_BINDING_TABLE
|
223 .cache
= (CACHE_NEW_SAMPLER
|
226 .emit
= upload_ps_state
,