src/mesa/drivers/dri/i965/gen7_wm_state.c

   1 /*
   2  * Copyright © 2011 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include <stdbool.h>
  25 #include "brw_context.h"
  26 #include "brw_state.h"
  27 #include "brw_defines.h"
  28 #include "brw_util.h"
  29 #include "brw_wm.h"
  30 #include "program/prog_parameter.h"
  31 #include "program/prog_statevars.h"
  32 #include "intel_batchbuffer.h"
  33
  34 static void
  35 upload_wm_state(struct brw_context *brw)
  36 {
  37    struct intel_context *intel = &brw->intel;
  38    struct gl_context *ctx = &intel->ctx;
  39    const struct brw_fragment_program *fp =
  40       brw_fragment_program_const(brw->fragment_program);
  41    bool writes_depth = false;
  42    bool multisampled_fbo = false;
  43    uint32_t dw1, dw2;
  44
  45    /* _NEW_BUFFERS */
  46    if (ctx->DrawBuffer->_ColorDrawBuffers[0])
  47       multisampled_fbo = ctx->DrawBuffer->_ColorDrawBuffers[0]->NumSamples > 0;
  48
  49    dw1 = dw2 = 0;
  50    dw1 |= GEN7_WM_STATISTICS_ENABLE;
  51    dw1 |= GEN7_WM_LINE_AA_WIDTH_1_0;
  52    dw1 |= GEN7_WM_LINE_END_CAP_AA_WIDTH_0_5;
  53
  54    /* _NEW_LINE */
  55    if (ctx->Line.StippleFlag)
  56       dw1 |= GEN7_WM_LINE_STIPPLE_ENABLE;
  57
  58    /* _NEW_POLYGON */
  59    if (ctx->Polygon.StippleFlag)
  60       dw1 |= GEN7_WM_POLYGON_STIPPLE_ENABLE;
  61
  62    /* BRW_NEW_FRAGMENT_PROGRAM */
  63    if (fp->program.Base.InputsRead & FRAG_BIT_WPOS)
  64       dw1 |= GEN7_WM_USES_SOURCE_DEPTH | GEN7_WM_USES_SOURCE_W;
  65    if (fp->program.Base.OutputsWritten & BITFIELD64_BIT(FRAG_RESULT_DEPTH)) {
  66       writes_depth = true;
  67       dw1 |= GEN7_WM_PSCDEPTH_ON;
  68    }
  69    /* CACHE_NEW_WM_PROG */
  70    dw1 |= brw->wm.prog_data->barycentric_interp_modes <<
  71       GEN7_WM_BARYCENTRIC_INTERPOLATION_MODE_SHIFT;
  72
  73    /* _NEW_COLOR */
  74    if (fp->program.UsesKill || ctx->Color.AlphaEnabled)
  75       dw1 |= GEN7_WM_KILL_ENABLE;
  76
  77    /* _NEW_BUFFERS */
  78    if (brw_color_buffer_write_enabled(brw) || writes_depth ||
  79        dw1 & GEN7_WM_KILL_ENABLE) {
  80       dw1 |= GEN7_WM_DISPATCH_ENABLE;
  81    }
  82    if (multisampled_fbo) {
  83       /* _NEW_MULTISAMPLE */
  84       if (ctx->Multisample.Enabled)
  85          dw1 |= GEN7_WM_MSRAST_ON_PATTERN;
  86       else
  87          dw1 |= GEN7_WM_MSRAST_OFF_PIXEL;
  88       dw2 |= GEN7_WM_MSDISPMODE_PERPIXEL;
  89    } else {
  90       dw1 |= GEN7_WM_MSRAST_OFF_PIXEL;
  91       dw2 |= GEN7_WM_MSDISPMODE_PERSAMPLE;
  92    }
  93
  94    BEGIN_BATCH(3);
  95    OUT_BATCH(_3DSTATE_WM << 16 | (3 - 2));
  96    OUT_BATCH(dw1);
  97    OUT_BATCH(dw2);
  98    ADVANCE_BATCH();
  99 }
 100
 101 const struct brw_tracked_state gen7_wm_state = {
 102    .dirty = {
 103       .mesa  = (_NEW_LINE | _NEW_POLYGON |
 104                 _NEW_COLOR | _NEW_BUFFERS |
 105                 _NEW_MULTISAMPLE),
 106       .brw   = (BRW_NEW_FRAGMENT_PROGRAM |
 107                 BRW_NEW_BATCH),
 108       .cache = CACHE_NEW_WM_PROG,
 109    },
 110    .emit = upload_wm_state,
 111 };
 112
 113 static void
 114 upload_ps_state(struct brw_context *brw)
 115 {
 116    struct intel_context *intel = &brw->intel;
 117    struct gl_context *ctx = &intel->ctx;
 118    uint32_t dw2, dw4, dw5;
 119    const int max_threads_shift = brw->intel.is_haswell ?
 120       HSW_PS_MAX_THREADS_SHIFT : IVB_PS_MAX_THREADS_SHIFT;
 121
 122    /* BRW_NEW_PS_BINDING_TABLE */
 123    BEGIN_BATCH(2);
 124    OUT_BATCH(_3DSTATE_BINDING_TABLE_POINTERS_PS << 16 | (2 - 2));
 125    OUT_BATCH(brw->wm.bind_bo_offset);
 126    ADVANCE_BATCH();
 127
 128    /* CACHE_NEW_SAMPLER */
 129    BEGIN_BATCH(2);
 130    OUT_BATCH(_3DSTATE_SAMPLER_STATE_POINTERS_PS << 16 | (2 - 2));
 131    OUT_BATCH(brw->sampler.offset);
 132    ADVANCE_BATCH();
 133
 134    /* CACHE_NEW_WM_PROG */
 135    if (brw->wm.prog_data->nr_params == 0) {
 136       /* Disable the push constant buffers. */
 137       BEGIN_BATCH(7);
 138       OUT_BATCH(_3DSTATE_CONSTANT_PS << 16 | (7 - 2));
 139       OUT_BATCH(0);
 140       OUT_BATCH(0);
 141       OUT_BATCH(0);
 142       OUT_BATCH(0);
 143       OUT_BATCH(0);
 144       OUT_BATCH(0);
 145       ADVANCE_BATCH();
 146    } else {
 147       BEGIN_BATCH(7);
 148       OUT_BATCH(_3DSTATE_CONSTANT_PS << 16 | (7 - 2));
 149
 150       OUT_BATCH(ALIGN(brw->wm.prog_data->nr_params,
 151                       brw->wm.prog_data->dispatch_width) / 8);
 152       OUT_BATCH(0);
 153       /* Pointer to the WM constant buffer.  Covered by the set of
 154        * state flags from gen6_upload_wm_push_constants.
 155        */
 156       OUT_BATCH(brw->wm.push_const_offset);
 157       OUT_BATCH(0);
 158       OUT_BATCH(0);
 159       OUT_BATCH(0);
 160       ADVANCE_BATCH();
 161    }
 162
 163    dw2 = dw4 = dw5 = 0;
 164
 165    /* CACHE_NEW_SAMPLER */
 166    dw2 |= (ALIGN(brw->sampler.count, 4) / 4) << GEN7_PS_SAMPLER_COUNT_SHIFT;
 167
 168    /* Use ALT floating point mode for ARB fragment programs, because they
 169     * require 0^0 == 1.  Even though _CurrentFragmentProgram is used for
 170     * rendering, CurrentFragmentProgram is used for this check to
 171     * differentiate between the GLSL and non-GLSL cases.
 172     */
 173    if (intel->ctx.Shader.CurrentFragmentProgram == NULL)
 174       dw2 |= GEN7_PS_FLOATING_POINT_MODE_ALT;
 175
 176    if (intel->is_haswell)
 177       dw4 |= SET_FIELD(1, HSW_PS_SAMPLE_MASK); /* 1 sample for now */
 178
 179    dw4 |= (brw->max_wm_threads - 1) << max_threads_shift;
 180
 181    /* CACHE_NEW_WM_PROG */
 182    if (brw->wm.prog_data->nr_params > 0)
 183       dw4 |= GEN7_PS_PUSH_CONSTANT_ENABLE;
 184
 185    /* CACHE_NEW_WM_PROG | _NEW_COLOR
 186     *
 187     * The hardware wedges if you have this bit set but don't turn on any dual
 188     * source blend factors.
 189     */
 190    if (brw->wm.prog_data->dual_src_blend &&
 191        (ctx->Color.BlendEnabled & 1) &&
 192        ctx->Color.Blend[0]._UsesDualSrc) {
 193       dw4 |= GEN7_PS_DUAL_SOURCE_BLEND_ENABLE;
 194    }
 195
 196    /* BRW_NEW_FRAGMENT_PROGRAM */
 197    if (brw->fragment_program->Base.InputsRead != 0)
 198       dw4 |= GEN7_PS_ATTRIBUTE_ENABLE;
 199
 200    if (brw->wm.prog_data->dispatch_width == 8) {
 201       dw4 |= GEN7_PS_8_DISPATCH_ENABLE;
 202       if (brw->wm.prog_data->prog_offset_16)
 203          dw4 |= GEN7_PS_16_DISPATCH_ENABLE;
 204    } else {
 205       dw4 |= GEN7_PS_16_DISPATCH_ENABLE;
 206    }
 207
 208    dw5 |= (brw->wm.prog_data->first_curbe_grf <<
 209            GEN7_PS_DISPATCH_START_GRF_SHIFT_0);
 210    dw5 |= (brw->wm.prog_data->first_curbe_grf_16 <<
 211            GEN7_PS_DISPATCH_START_GRF_SHIFT_2);
 212
 213    BEGIN_BATCH(8);
 214    OUT_BATCH(_3DSTATE_PS << 16 | (8 - 2));
 215    OUT_BATCH(brw->wm.prog_offset);
 216    OUT_BATCH(dw2);
 217    if (brw->wm.prog_data->total_scratch) {
 218       OUT_RELOC(brw->wm.scratch_bo,
 219                 I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
 220                 ffs(brw->wm.prog_data->total_scratch) - 11);
 221    } else {
 222       OUT_BATCH(0);
 223    }
 224    OUT_BATCH(dw4);
 225    OUT_BATCH(dw5);
 226    OUT_BATCH(0); /* kernel 1 pointer */
 227    OUT_BATCH(brw->wm.prog_offset + brw->wm.prog_data->prog_offset_16);
 228    ADVANCE_BATCH();
 229 }
 230
 231 const struct brw_tracked_state gen7_ps_state = {
 232    .dirty = {
 233       .mesa  = (_NEW_PROGRAM_CONSTANTS |
 234                 _NEW_COLOR),
 235       .brw   = (BRW_NEW_FRAGMENT_PROGRAM |
 236                 BRW_NEW_PS_BINDING_TABLE |
 237                 BRW_NEW_BATCH),
 238       .cache = (CACHE_NEW_SAMPLER |
 239                 CACHE_NEW_WM_PROG)
 240    },
 241    .emit = upload_ps_state,
 242 };