2 * Copyright © 2011 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
23 #include "main/mtypes.h"
24 #include "main/samplerobj.h"
25 #include "program/prog_parameter.h"
27 #include "intel_mipmap_tree.h"
28 #include "intel_batchbuffer.h"
29 #include "intel_tex.h"
30 #include "intel_fbo.h"
32 #include "brw_context.h"
33 #include "brw_state.h"
34 #include "brw_defines.h"
38 gen7_set_surface_tiling(struct gen7_surface_state
*surf
, uint32_t tiling
)
41 case I915_TILING_NONE
:
42 surf
->ss0
.tiled_surface
= 0;
43 surf
->ss0
.tile_walk
= 0;
46 surf
->ss0
.tiled_surface
= 1;
47 surf
->ss0
.tile_walk
= BRW_TILEWALK_XMAJOR
;
50 surf
->ss0
.tiled_surface
= 1;
51 surf
->ss0
.tile_walk
= BRW_TILEWALK_YMAJOR
;
57 gen7_update_texture_surface(struct gl_context
*ctx
, GLuint unit
)
59 struct brw_context
*brw
= brw_context(ctx
);
60 struct gl_texture_object
*tObj
= ctx
->Texture
.Unit
[unit
]._Current
;
61 struct intel_texture_object
*intelObj
= intel_texture_object(tObj
);
62 struct intel_mipmap_tree
*mt
= intelObj
->mt
;
63 struct gl_texture_image
*firstImage
= tObj
->Image
[0][tObj
->BaseLevel
];
64 struct gl_sampler_object
*sampler
= _mesa_get_samplerobj(ctx
, unit
);
65 const GLuint surf_index
= SURF_INDEX_TEXTURE(unit
);
66 struct gen7_surface_state
*surf
;
67 int width
, height
, depth
;
69 intel_miptree_get_dimensions_for_image(firstImage
, &width
, &height
, &depth
);
71 surf
= brw_state_batch(brw
, AUB_TRACE_SURFACE_STATE
,
72 sizeof(*surf
), 32, &brw
->bind
.surf_offset
[surf_index
]);
73 memset(surf
, 0, sizeof(*surf
));
76 surf
->ss0
.vertical_alignment
= 1;
78 surf
->ss0
.surface_type
= translate_tex_target(tObj
->Target
);
79 surf
->ss0
.surface_format
= translate_tex_format(mt
->format
,
80 firstImage
->InternalFormat
,
83 if (tObj
->Target
== GL_TEXTURE_CUBE_MAP
) {
84 surf
->ss0
.cube_pos_x
= 1;
85 surf
->ss0
.cube_pos_y
= 1;
86 surf
->ss0
.cube_pos_z
= 1;
87 surf
->ss0
.cube_neg_x
= 1;
88 surf
->ss0
.cube_neg_y
= 1;
89 surf
->ss0
.cube_neg_z
= 1;
92 surf
->ss0
.is_array
= depth
> 1 && tObj
->Target
!= GL_TEXTURE_3D
;
94 gen7_set_surface_tiling(surf
, intelObj
->mt
->region
->tiling
);
96 /* ss0 remaining fields:
97 * - vertical_alignment
98 * - horizontal_alignment
99 * - vert_line_stride (exists on gen6 but we ignore it)
100 * - vert_line_stride_ofs (exists on gen6 but we ignore it)
101 * - surface_array_spacing
102 * - render_cache_read_write (exists on gen6 but ignored here)
105 surf
->ss1
.base_addr
= intelObj
->mt
->region
->bo
->offset
; /* reloc */
107 surf
->ss2
.width
= width
- 1;
108 surf
->ss2
.height
= height
- 1;
110 surf
->ss3
.pitch
= (intelObj
->mt
->region
->pitch
* intelObj
->mt
->cpp
) - 1;
111 surf
->ss3
.depth
= depth
- 1;
115 surf
->ss5
.mip_count
= intelObj
->_MaxLevel
- tObj
->BaseLevel
;
116 surf
->ss5
.min_lod
= 0;
118 /* ss5 remaining fields:
119 * - x_offset (N/A for textures?)
124 /* Emit relocation to surface contents */
125 drm_intel_bo_emit_reloc(brw
->intel
.batch
.bo
,
126 brw
->bind
.surf_offset
[surf_index
] +
127 offsetof(struct gen7_surface_state
, ss1
),
128 intelObj
->mt
->region
->bo
, 0,
129 I915_GEM_DOMAIN_SAMPLER
, 0);
133 * Create the constant buffer surface. Vertex/fragment shader constants will
134 * be read from this buffer with Data Port Read instructions/messages.
137 gen7_create_constant_surface(struct brw_context
*brw
,
140 uint32_t *out_offset
)
142 const GLint w
= width
- 1;
143 struct gen7_surface_state
*surf
;
145 surf
= brw_state_batch(brw
, AUB_TRACE_SURFACE_STATE
,
146 sizeof(*surf
), 32, out_offset
);
147 memset(surf
, 0, sizeof(*surf
));
149 surf
->ss0
.surface_type
= BRW_SURFACE_BUFFER
;
150 surf
->ss0
.surface_format
= BRW_SURFACEFORMAT_R32G32B32A32_FLOAT
;
152 surf
->ss0
.render_cache_read_write
= 1;
155 surf
->ss1
.base_addr
= bo
->offset
; /* reloc */
157 surf
->ss2
.width
= w
& 0x7f; /* bits 6:0 of size or width */
158 surf
->ss2
.height
= (w
>> 7) & 0x1fff; /* bits 19:7 of size or width */
159 surf
->ss3
.depth
= (w
>> 20) & 0x7f; /* bits 26:20 of size or width */
160 surf
->ss3
.pitch
= (width
* 16) - 1; /* ignored?? */
161 gen7_set_surface_tiling(surf
, I915_TILING_NONE
); /* tiling now allowed */
163 /* Emit relocation to surface contents. Section 5.1.1 of the gen4
164 * bspec ("Data Cache") says that the data cache does not exist as
165 * a separate cache and is just the sampler cache.
167 drm_intel_bo_emit_reloc(brw
->intel
.batch
.bo
,
169 offsetof(struct gen7_surface_state
, ss1
)),
171 I915_GEM_DOMAIN_SAMPLER
, 0);
175 gen7_update_null_renderbuffer_surface(struct brw_context
*brw
, unsigned unit
)
177 struct gen7_surface_state
*surf
;
179 surf
= brw_state_batch(brw
, AUB_TRACE_SURFACE_STATE
,
180 sizeof(*surf
), 32, &brw
->bind
.surf_offset
[unit
]);
181 memset(surf
, 0, sizeof(*surf
));
183 surf
->ss0
.surface_type
= BRW_SURFACE_NULL
;
184 surf
->ss0
.surface_format
= BRW_SURFACEFORMAT_B8G8R8A8_UNORM
;
188 * Sets up a surface state structure to point at the given region.
189 * While it is only used for the front/back buffer currently, it should be
190 * usable for further buffers when doing ARB_draw_buffer support.
193 gen7_update_renderbuffer_surface(struct brw_context
*brw
,
194 struct gl_renderbuffer
*rb
,
197 struct intel_context
*intel
= &brw
->intel
;
198 struct gl_context
*ctx
= &intel
->ctx
;
199 struct intel_renderbuffer
*irb
= intel_renderbuffer(rb
);
200 struct intel_region
*region
= irb
->mt
->region
;
201 struct gen7_surface_state
*surf
;
202 uint32_t tile_x
, tile_y
;
204 surf
= brw_state_batch(brw
, AUB_TRACE_SURFACE_STATE
,
205 sizeof(*surf
), 32, &brw
->bind
.surf_offset
[unit
]);
206 memset(surf
, 0, sizeof(*surf
));
208 if (irb
->mt
->align_h
== 4)
209 surf
->ss0
.vertical_alignment
= 1;
211 switch (irb
->Base
.Format
) {
212 case MESA_FORMAT_SARGB8
:
213 /* without GL_EXT_framebuffer_sRGB we shouldn't bind sRGB
214 surfaces to the blend/update as sRGB */
215 if (ctx
->Color
.sRGBEnabled
)
216 surf
->ss0
.surface_format
= brw_format_for_mesa_format(irb
->Base
.Format
);
218 surf
->ss0
.surface_format
= BRW_SURFACEFORMAT_B8G8R8A8_UNORM
;
221 assert(brw_render_target_supported(intel
, irb
->Base
.Format
));
222 surf
->ss0
.surface_format
= brw
->render_target_format
[irb
->Base
.Format
];
223 if (unlikely(!brw
->format_supported_as_render_target
[irb
->Base
.Format
])) {
224 _mesa_problem(ctx
, "%s: renderbuffer format %s unsupported\n",
225 __FUNCTION__
, _mesa_get_format_name(irb
->Base
.Format
));
230 surf
->ss0
.surface_type
= BRW_SURFACE_2D
;
232 surf
->ss1
.base_addr
= intel_renderbuffer_tile_offsets(irb
, &tile_x
, &tile_y
);
233 surf
->ss1
.base_addr
+= region
->bo
->offset
; /* reloc */
235 assert(brw
->has_surface_tile_offset
);
236 /* Note that the low bits of these fields are missing, so
237 * there's the possibility of getting in trouble.
239 assert(tile_x
% 4 == 0);
240 assert(tile_y
% 2 == 0);
241 surf
->ss5
.x_offset
= tile_x
/ 4;
242 surf
->ss5
.y_offset
= tile_y
/ 2;
244 surf
->ss2
.width
= rb
->Width
- 1;
245 surf
->ss2
.height
= rb
->Height
- 1;
246 gen7_set_surface_tiling(surf
, region
->tiling
);
247 surf
->ss3
.pitch
= (region
->pitch
* region
->cpp
) - 1;
249 drm_intel_bo_emit_reloc(brw
->intel
.batch
.bo
,
250 brw
->bind
.surf_offset
[unit
] +
251 offsetof(struct gen7_surface_state
, ss1
),
253 surf
->ss1
.base_addr
- region
->bo
->offset
,
254 I915_GEM_DOMAIN_RENDER
,
255 I915_GEM_DOMAIN_RENDER
);
259 gen7_init_vtable_surface_functions(struct brw_context
*brw
)
261 struct intel_context
*intel
= &brw
->intel
;
263 intel
->vtbl
.update_texture_surface
= gen7_update_texture_surface
;
264 intel
->vtbl
.update_renderbuffer_surface
= gen7_update_renderbuffer_surface
;
265 intel
->vtbl
.update_null_renderbuffer_surface
=
266 gen7_update_null_renderbuffer_surface
;
267 intel
->vtbl
.create_constant_surface
= gen7_create_constant_surface
;