src/mesa/drivers/dri/i965/gen7_wm_surface_state.c

   1 /*
   2  * Copyright © 2011 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23 #include "main/mtypes.h"
  24 #include "main/blend.h"
  25 #include "main/samplerobj.h"
  26 #include "main/texformat.h"
  27 #include "program/prog_parameter.h"
  28
  29 #include "intel_mipmap_tree.h"
  30 #include "intel_batchbuffer.h"
  31 #include "intel_tex.h"
  32 #include "intel_fbo.h"
  33 #include "intel_buffer_objects.h"
  34
  35 #include "brw_context.h"
  36 #include "brw_state.h"
  37 #include "brw_defines.h"
  38 #include "brw_wm.h"
  39
  40 /**
  41  * Convert an swizzle enumeration (i.e. SWIZZLE_X) to one of the Gen7.5+
  42  * "Shader Channel Select" enumerations (i.e. HSW_SCS_RED)
  43  */
  44 static unsigned
  45 swizzle_to_scs(GLenum swizzle)
  46 {
  47    switch (swizzle) {
  48    case SWIZZLE_X:
  49       return HSW_SCS_RED;
  50    case SWIZZLE_Y:
  51       return HSW_SCS_GREEN;
  52    case SWIZZLE_Z:
  53       return HSW_SCS_BLUE;
  54    case SWIZZLE_W:
  55       return HSW_SCS_ALPHA;
  56    case SWIZZLE_ZERO:
  57       return HSW_SCS_ZERO;
  58    case SWIZZLE_ONE:
  59       return HSW_SCS_ONE;
  60    }
  61
  62    assert(!"Should not get here: invalid swizzle mode");
  63    return HSW_SCS_ZERO;
  64 }
  65
  66 uint32_t
  67 gen7_surface_tiling_mode(uint32_t tiling)
  68 {
  69    switch (tiling) {
  70    case I915_TILING_X:
  71       return GEN7_SURFACE_TILING_X;
  72    case I915_TILING_Y:
  73       return GEN7_SURFACE_TILING_Y;
  74    default:
  75       return GEN7_SURFACE_TILING_NONE;
  76    }
  77 }
  78
  79
  80 uint32_t
  81 gen7_surface_msaa_bits(unsigned num_samples, enum intel_msaa_layout layout)
  82 {
  83    uint32_t ss4 = 0;
  84
  85    if (num_samples > 4)
  86       ss4 |= GEN7_SURFACE_MULTISAMPLECOUNT_8;
  87    else if (num_samples > 1)
  88       ss4 |= GEN7_SURFACE_MULTISAMPLECOUNT_4;
  89    else
  90       ss4 |= GEN7_SURFACE_MULTISAMPLECOUNT_1;
  91
  92    if (layout == INTEL_MSAA_LAYOUT_IMS)
  93       ss4 |= GEN7_SURFACE_MSFMT_DEPTH_STENCIL;
  94    else
  95       ss4 |= GEN7_SURFACE_MSFMT_MSS;
  96
  97    return ss4;
  98 }
  99
 100
 101 void
 102 gen7_set_surface_mcs_info(struct brw_context *brw,
 103                           uint32_t *surf,
 104                           uint32_t surf_offset,
 105                           const struct intel_mipmap_tree *mcs_mt,
 106                           bool is_render_target)
 107 {
 108    /* From the Ivy Bridge PRM, Vol4 Part1 p76, "MCS Base Address":
 109     *
 110     *     "The MCS surface must be stored as Tile Y."
 111     */
 112    assert(mcs_mt->region->tiling == I915_TILING_Y);
 113
 114    /* Compute the pitch in units of tiles.  To do this we need to divide the
 115     * pitch in bytes by 128, since a single Y-tile is 128 bytes wide.
 116     */
 117    unsigned pitch_tiles = mcs_mt->region->pitch / 128;
 118
 119    /* The upper 20 bits of surface state DWORD 6 are the upper 20 bits of the
 120     * GPU address of the MCS buffer; the lower 12 bits contain other control
 121     * information.  Since buffer addresses are always on 4k boundaries (and
 122     * thus have their lower 12 bits zero), we can use an ordinary reloc to do
 123     * the necessary address translation.
 124     */
 125    assert ((mcs_mt->region->bo->offset & 0xfff) == 0);
 126
 127    surf[6] = GEN7_SURFACE_MCS_ENABLE |
 128              SET_FIELD(pitch_tiles - 1, GEN7_SURFACE_MCS_PITCH) |
 129              mcs_mt->region->bo->offset;
 130
 131    drm_intel_bo_emit_reloc(brw->batch.bo,
 132                            surf_offset + 6 * 4,
 133                            mcs_mt->region->bo,
 134                            surf[6] & 0xfff,
 135                            is_render_target ? I915_GEM_DOMAIN_RENDER
 136                            : I915_GEM_DOMAIN_SAMPLER,
 137                            is_render_target ? I915_GEM_DOMAIN_RENDER : 0);
 138 }
 139
 140
 141 void
 142 gen7_check_surface_setup(uint32_t *surf, bool is_render_target)
 143 {
 144    unsigned num_multisamples = surf[4] & INTEL_MASK(5, 3);
 145    unsigned multisampled_surface_storage_format = surf[4] & (1 << 6);
 146    unsigned surface_array_spacing = surf[0] & (1 << 10);
 147    bool is_multisampled = num_multisamples != GEN7_SURFACE_MULTISAMPLECOUNT_1;
 148
 149    (void) surface_array_spacing;
 150
 151    /* From the Ivybridge PRM, Volume 4 Part 1, page 66 (RENDER_SURFACE_STATE
 152     * dword 0 bit 10 "Surface Array Spacing" Programming Notes):
 153     *
 154     *   If Multisampled Surface Storage Format is MSFMT_MSS and Number of
 155     *   Multisamples is not MULTISAMPLECOUNT_1, this field must be set to
 156     *   ARYSPC_LOD0.
 157     */
 158    if (multisampled_surface_storage_format == GEN7_SURFACE_MSFMT_MSS
 159        && is_multisampled)
 160       assert(surface_array_spacing == GEN7_SURFACE_ARYSPC_LOD0);
 161
 162    /* From the Ivybridge PRM, Volume 4 Part 1, page 72 (RENDER_SURFACE_STATE
 163     * dword 4 bit 6 "Multisampled Surface Storage" Programming Notes):
 164     *
 165     *   All multisampled render target surfaces must have this field set to
 166     *   MSFMT_MSS.
 167     *
 168     * But also:
 169     *
 170     *   This field is ignored if Number of Multisamples is MULTISAMPLECOUNT_1.
 171     */
 172    if (is_render_target && is_multisampled) {
 173       assert(multisampled_surface_storage_format == GEN7_SURFACE_MSFMT_MSS);
 174    }
 175
 176    /* From the Ivybridge PRM, Volume 4 Part 1, page 72 (RENDER_SURFACE_STATE
 177     * dword 4 bit 6 "Multisampled Surface Storage Format" Errata):
 178     *
 179     *   If the surface’s Number of Multisamples is MULTISAMPLECOUNT_8, Width
 180     *   is >= 8192 (meaning the actual surface width is >= 8193 pixels), this
 181     *   field must be set to MSFMT_MSS.
 182     */
 183    uint32_t width = GET_FIELD(surf[2], GEN7_SURFACE_WIDTH) + 1;
 184    if (num_multisamples == GEN7_SURFACE_MULTISAMPLECOUNT_8 && width >= 8193) {
 185       assert(multisampled_surface_storage_format == GEN7_SURFACE_MSFMT_MSS);
 186    }
 187
 188    /* From the Ivybridge PRM, Volume 4 Part 1, page 72 (RENDER_SURFACE_STATE
 189     * dword 4 bit 6 "Multisampled Surface Storage Format" Errata):
 190     *
 191     *   If the surface’s Number of Multisamples is MULTISAMPLECOUNT_8,
 192     *   ((Depth+1) * (Height+1)) is > 4,194,304, OR if the surface’s Number of
 193     *   Multisamples is MULTISAMPLECOUNT_4, ((Depth+1) * (Height+1)) is >
 194     *   8,388,608, this field must be set to MSFMT_DEPTH_STENCIL.This field
 195     *   must be set to MSFMT_DEPTH_STENCIL if Surface Format is one of the
 196     *   following: I24X8_UNORM, L24X8_UNORM, A24X8_UNORM, or
 197     *   R24_UNORM_X8_TYPELESS.
 198     *
 199     * But also (from the Programming Notes):
 200     *
 201     *   This field is ignored if Number of Multisamples is MULTISAMPLECOUNT_1.
 202     */
 203    uint32_t depth = GET_FIELD(surf[3], BRW_SURFACE_DEPTH) + 1;
 204    uint32_t height = GET_FIELD(surf[2], GEN7_SURFACE_HEIGHT) + 1;
 205    if (num_multisamples == GEN7_SURFACE_MULTISAMPLECOUNT_8 &&
 206        depth * height > 4194304) {
 207       assert(multisampled_surface_storage_format ==
 208              GEN7_SURFACE_MSFMT_DEPTH_STENCIL);
 209    }
 210    if (num_multisamples == GEN7_SURFACE_MULTISAMPLECOUNT_4 &&
 211        depth * height > 8388608) {
 212       assert(multisampled_surface_storage_format ==
 213              GEN7_SURFACE_MSFMT_DEPTH_STENCIL);
 214    }
 215    if (is_multisampled) {
 216       switch (GET_FIELD(surf[0], BRW_SURFACE_FORMAT)) {
 217       case BRW_SURFACEFORMAT_I24X8_UNORM:
 218       case BRW_SURFACEFORMAT_L24X8_UNORM:
 219       case BRW_SURFACEFORMAT_A24X8_UNORM:
 220       case BRW_SURFACEFORMAT_R24_UNORM_X8_TYPELESS:
 221          assert(multisampled_surface_storage_format ==
 222                 GEN7_SURFACE_MSFMT_DEPTH_STENCIL);
 223       }
 224    }
 225 }
 226
 227
 228 static void
 229 gen7_update_buffer_texture_surface(struct gl_context *ctx,
 230                                    unsigned unit,
 231                                    uint32_t *surf_offset)
 232 {
 233    struct brw_context *brw = brw_context(ctx);
 234    struct gl_texture_object *tObj = ctx->Texture.Unit[unit]._Current;
 235    struct intel_buffer_object *intel_obj =
 236       intel_buffer_object(tObj->BufferObject);
 237    drm_intel_bo *bo = intel_obj ? intel_obj->buffer : NULL;
 238    gl_format format = tObj->_BufferObjectFormat;
 239
 240    uint32_t *surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE,
 241                                     8 * 4, 32, surf_offset);
 242    memset(surf, 0, 8 * 4);
 243
 244    uint32_t surface_format = brw_format_for_mesa_format(format);
 245    if (surface_format == 0 && format != MESA_FORMAT_RGBA_FLOAT32) {
 246       _mesa_problem(NULL, "bad format %s for texture buffer\n",
 247                     _mesa_get_format_name(format));
 248    }
 249
 250    surf[0] = BRW_SURFACE_BUFFER << BRW_SURFACE_TYPE_SHIFT |
 251              surface_format << BRW_SURFACE_FORMAT_SHIFT |
 252              BRW_SURFACE_RC_READ_WRITE;
 253
 254    if (bo) {
 255       surf[1] = bo->offset; /* reloc */
 256
 257       drm_intel_bo_emit_reloc(brw->batch.bo,
 258                               *surf_offset + 4,
 259                               bo, 0,
 260                               I915_GEM_DOMAIN_SAMPLER, 0);
 261
 262       int texel_size = _mesa_get_format_bytes(format);
 263       int w = intel_obj->Base.Size / texel_size;
 264
 265       /* note that these differ from GEN6 */
 266       surf[2] = SET_FIELD(w & 0x7f, GEN7_SURFACE_WIDTH) | /* bits 6:0 of size */
 267                 SET_FIELD((w >> 7) & 0x3fff, GEN7_SURFACE_HEIGHT); /* 20:7 */
 268       surf[3] = SET_FIELD((w >> 21) & 0x3f, BRW_SURFACE_DEPTH) | /* bits 26:21 */
 269                 (texel_size - 1);
 270    }
 271
 272    gen7_check_surface_setup(surf, false /* is_render_target */);
 273 }
 274
 275 static void
 276 gen7_update_texture_surface(struct gl_context *ctx,
 277                             unsigned unit,
 278                             uint32_t *surf_offset)
 279 {
 280    struct brw_context *brw = brw_context(ctx);
 281    struct gl_texture_object *tObj = ctx->Texture.Unit[unit]._Current;
 282    struct intel_texture_object *intelObj = intel_texture_object(tObj);
 283    struct intel_mipmap_tree *mt = intelObj->mt;
 284    struct gl_texture_image *firstImage = tObj->Image[0][tObj->BaseLevel];
 285    struct intel_texture_image *intel_image = intel_texture_image(firstImage);
 286    struct gl_sampler_object *sampler = _mesa_get_samplerobj(ctx, unit);
 287
 288    if (tObj->Target == GL_TEXTURE_BUFFER) {
 289       gen7_update_buffer_texture_surface(ctx, unit, surf_offset);
 290       return;
 291    }
 292
 293    uint32_t *surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE,
 294                                     8 * 4, 32, surf_offset);
 295    memset(surf, 0, 8 * 4);
 296
 297    uint32_t tex_format = translate_tex_format(brw,
 298                                               mt->format,
 299                                               tObj->DepthMode,
 300                                               sampler->sRGBDecode);
 301
 302    surf[0] = translate_tex_target(tObj->Target) << BRW_SURFACE_TYPE_SHIFT |
 303              tex_format << BRW_SURFACE_FORMAT_SHIFT |
 304              gen7_surface_tiling_mode(mt->region->tiling) |
 305              BRW_SURFACE_CUBEFACE_ENABLES;
 306
 307    if (mt->align_h == 4)
 308       surf[0] |= GEN7_SURFACE_VALIGN_4;
 309    if (mt->align_w == 8)
 310       surf[0] |= GEN7_SURFACE_HALIGN_8;
 311
 312    if (mt->logical_depth0 > 1 && tObj->Target != GL_TEXTURE_3D)
 313       surf[0] |= GEN7_SURFACE_IS_ARRAY;
 314
 315    if (mt->array_spacing_lod0)
 316       surf[0] |= GEN7_SURFACE_ARYSPC_LOD0;
 317
 318    surf[1] = mt->region->bo->offset + mt->offset; /* reloc */
 319
 320    surf[2] = SET_FIELD(mt->logical_width0 - 1, GEN7_SURFACE_WIDTH) |
 321              SET_FIELD(mt->logical_height0 - 1, GEN7_SURFACE_HEIGHT);
 322    surf[3] = SET_FIELD(mt->logical_depth0 - 1, BRW_SURFACE_DEPTH) |
 323              ((intelObj->mt->region->pitch) - 1);
 324
 325    surf[4] = gen7_surface_msaa_bits(mt->num_samples, mt->msaa_layout);
 326
 327    surf[5] = (SET_FIELD(GEN7_MOCS_L3, GEN7_SURFACE_MOCS) |
 328               /* mip count */
 329               (intelObj->_MaxLevel - intel_image->mt->first_level));
 330
 331    if (brw->is_haswell) {
 332       /* Handling GL_ALPHA as a surface format override breaks 1.30+ style
 333        * texturing functions that return a float, as our code generation always
 334        * selects the .x channel (which would always be 0).
 335        */
 336       const bool alpha_depth = tObj->DepthMode == GL_ALPHA &&
 337          (firstImage->_BaseFormat == GL_DEPTH_COMPONENT ||
 338           firstImage->_BaseFormat == GL_DEPTH_STENCIL);
 339
 340       const int swizzle = unlikely(alpha_depth)
 341          ? SWIZZLE_XYZW : brw_get_texture_swizzle(ctx, tObj);
 342
 343       surf[7] =
 344          SET_FIELD(swizzle_to_scs(GET_SWZ(swizzle, 0)), GEN7_SURFACE_SCS_R) |
 345          SET_FIELD(swizzle_to_scs(GET_SWZ(swizzle, 1)), GEN7_SURFACE_SCS_G) |
 346          SET_FIELD(swizzle_to_scs(GET_SWZ(swizzle, 2)), GEN7_SURFACE_SCS_B) |
 347          SET_FIELD(swizzle_to_scs(GET_SWZ(swizzle, 3)), GEN7_SURFACE_SCS_A);
 348    }
 349
 350    /* Emit relocation to surface contents */
 351    drm_intel_bo_emit_reloc(brw->batch.bo,
 352                            *surf_offset + 4,
 353                            intelObj->mt->region->bo,
 354                            surf[1] - intelObj->mt->region->bo->offset,
 355                            I915_GEM_DOMAIN_SAMPLER, 0);
 356
 357    gen7_check_surface_setup(surf, false /* is_render_target */);
 358 }
 359
 360 /**
 361  * Create the constant buffer surface.  Vertex/fragment shader constants will
 362  * be read from this buffer with Data Port Read instructions/messages.
 363  */
 364 static void
 365 gen7_create_constant_surface(struct brw_context *brw,
 366                              drm_intel_bo *bo,
 367                              uint32_t offset,
 368                              uint32_t size,
 369                              uint32_t *out_offset,
 370                              bool dword_pitch)
 371 {
 372    uint32_t stride = dword_pitch ? 4 : 16;
 373    uint32_t elements = ALIGN(size, stride) / stride;
 374    const GLint w = elements - 1;
 375
 376    uint32_t *surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE,
 377                                     8 * 4, 32, out_offset);
 378    memset(surf, 0, 8 * 4);
 379
 380    surf[0] = BRW_SURFACE_BUFFER << BRW_SURFACE_TYPE_SHIFT |
 381              BRW_SURFACEFORMAT_R32G32B32A32_FLOAT << BRW_SURFACE_FORMAT_SHIFT |
 382              BRW_SURFACE_RC_READ_WRITE;
 383
 384    assert(bo);
 385    surf[1] = bo->offset + offset; /* reloc */
 386
 387    /* note that these differ from GEN6 */
 388    surf[2] = SET_FIELD(w & 0x7f, GEN7_SURFACE_WIDTH) |
 389              SET_FIELD((w >> 7) & 0x3fff, GEN7_SURFACE_HEIGHT);
 390    surf[3] = SET_FIELD((w >> 21) & 0x3f, BRW_SURFACE_DEPTH) |
 391              (stride - 1);
 392
 393    if (brw->is_haswell) {
 394       surf[7] = SET_FIELD(HSW_SCS_RED,   GEN7_SURFACE_SCS_R) |
 395                 SET_FIELD(HSW_SCS_GREEN, GEN7_SURFACE_SCS_G) |
 396                 SET_FIELD(HSW_SCS_BLUE,  GEN7_SURFACE_SCS_B) |
 397                 SET_FIELD(HSW_SCS_ALPHA, GEN7_SURFACE_SCS_A);
 398    }
 399
 400    drm_intel_bo_emit_reloc(brw->batch.bo,
 401                            *out_offset + 4,
 402                            bo, offset,
 403                            I915_GEM_DOMAIN_SAMPLER, 0);
 404
 405    gen7_check_surface_setup(surf, false /* is_render_target */);
 406 }
 407
 408 /**
 409  * Create a surface for shader time.
 410  */
 411 void
 412 gen7_create_shader_time_surface(struct brw_context *brw, uint32_t *out_offset)
 413 {
 414    const int w = brw->shader_time.bo->size - 1;
 415
 416    uint32_t *surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE,
 417                                     8 * 4, 32, out_offset);
 418    memset(surf, 0, 8 * 4);
 419
 420    surf[0] = BRW_SURFACE_BUFFER << BRW_SURFACE_TYPE_SHIFT |
 421              BRW_SURFACEFORMAT_RAW << BRW_SURFACE_FORMAT_SHIFT |
 422              BRW_SURFACE_RC_READ_WRITE;
 423
 424    surf[1] = brw->shader_time.bo->offset; /* reloc */
 425
 426    /* note that these differ from GEN6 */
 427    surf[2] = SET_FIELD(w & 0x7f, GEN7_SURFACE_WIDTH) |
 428              SET_FIELD((w >> 7) & 0x3fff, GEN7_SURFACE_HEIGHT);
 429    surf[3] = SET_FIELD((w >> 21) & 0x3f, BRW_SURFACE_DEPTH);
 430
 431    /* Unlike texture or renderbuffer surfaces, we only do untyped operations
 432     * on the shader_time surface, so there's no need to set HSW channel
 433     * overrides.
 434     */
 435
 436    drm_intel_bo_emit_reloc(brw->batch.bo,
 437                            *out_offset + 4,
 438                            brw->shader_time.bo, 0,
 439                            I915_GEM_DOMAIN_SAMPLER, 0);
 440
 441    gen7_check_surface_setup(surf, false /* is_render_target */);
 442 }
 443
 444 static void
 445 gen7_update_null_renderbuffer_surface(struct brw_context *brw, unsigned unit)
 446 {
 447    /* From the Ivy bridge PRM, Vol4 Part1 p62 (Surface Type: Programming
 448     * Notes):
 449     *
 450     *     A null surface is used in instances where an actual surface is not
 451     *     bound. When a write message is generated to a null surface, no
 452     *     actual surface is written to. When a read message (including any
 453     *     sampling engine message) is generated to a null surface, the result
 454     *     is all zeros. Note that a null surface type is allowed to be used
 455     *     with all messages, even if it is not specificially indicated as
 456     *     supported. All of the remaining fields in surface state are ignored
 457     *     for null surfaces, with the following exceptions: Width, Height,
 458     *     Depth, LOD, and Render Target View Extent fields must match the
 459     *     depth buffer’s corresponding state for all render target surfaces,
 460     *     including null.
 461     */
 462    struct gl_context *ctx = &brw->ctx;
 463
 464    /* _NEW_BUFFERS */
 465    const struct gl_framebuffer *fb = ctx->DrawBuffer;
 466
 467    uint32_t *surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE, 8 * 4, 32,
 468                                     &brw->wm.base.surf_offset[SURF_INDEX_DRAW(unit)]);
 469    memset(surf, 0, 8 * 4);
 470
 471    /* From the Ivybridge PRM, Volume 4, Part 1, page 65,
 472     * Tiled Surface: Programming Notes:
 473     * "If Surface Type is SURFTYPE_NULL, this field must be TRUE."
 474     */
 475    surf[0] = BRW_SURFACE_NULL << BRW_SURFACE_TYPE_SHIFT |
 476              BRW_SURFACEFORMAT_B8G8R8A8_UNORM << BRW_SURFACE_FORMAT_SHIFT |
 477              GEN7_SURFACE_TILING_Y;
 478
 479    surf[2] = SET_FIELD(fb->Width - 1, GEN7_SURFACE_WIDTH) |
 480              SET_FIELD(fb->Height - 1, GEN7_SURFACE_HEIGHT);
 481
 482    gen7_check_surface_setup(surf, true /* is_render_target */);
 483 }
 484
 485 /**
 486  * Sets up a surface state structure to point at the given region.
 487  * While it is only used for the front/back buffer currently, it should be
 488  * usable for further buffers when doing ARB_draw_buffer support.
 489  */
 490 static void
 491 gen7_update_renderbuffer_surface(struct brw_context *brw,
 492                                  struct gl_renderbuffer *rb,
 493                                  bool layered,
 494                                  unsigned int unit)
 495 {
 496    struct gl_context *ctx = &brw->ctx;
 497    struct intel_renderbuffer *irb = intel_renderbuffer(rb);
 498    struct intel_region *region = irb->mt->region;
 499    uint32_t format;
 500    /* _NEW_BUFFERS */
 501    gl_format rb_format = _mesa_get_render_format(ctx, intel_rb_format(irb));
 502    uint32_t surftype;
 503    bool is_array = false;
 504    int depth = MAX2(rb->Depth, 1);
 505    int min_array_element;
 506    const uint8_t mocs = GEN7_MOCS_L3;
 507    GLenum gl_target = rb->TexImage ?
 508                          rb->TexImage->TexObject->Target : GL_TEXTURE_2D;
 509
 510    uint32_t surf_index = SURF_INDEX_DRAW(unit);
 511
 512    uint32_t *surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE, 8 * 4, 32,
 513                                     &brw->wm.base.surf_offset[surf_index]);
 514    memset(surf, 0, 8 * 4);
 515
 516    intel_miptree_used_for_rendering(irb->mt);
 517
 518    /* Render targets can't use IMS layout */
 519    assert(irb->mt->msaa_layout != INTEL_MSAA_LAYOUT_IMS);
 520
 521    assert(brw_render_target_supported(brw, rb));
 522    format = brw->render_target_format[rb_format];
 523    if (unlikely(!brw->format_supported_as_render_target[rb_format])) {
 524       _mesa_problem(ctx, "%s: renderbuffer format %s unsupported\n",
 525                     __FUNCTION__, _mesa_get_format_name(rb_format));
 526    }
 527
 528    switch (gl_target) {
 529    case GL_TEXTURE_CUBE_MAP_ARRAY:
 530    case GL_TEXTURE_CUBE_MAP:
 531       surftype = BRW_SURFACE_2D;
 532       is_array = true;
 533       depth *= 6;
 534       break;
 535    default:
 536       surftype = translate_tex_target(gl_target);
 537       is_array = _mesa_tex_target_is_array(gl_target);
 538       break;
 539    }
 540
 541    if (layered) {
 542       min_array_element = 0;
 543    } else if (irb->mt->num_samples > 1) {
 544       min_array_element = irb->mt_layer / irb->mt->num_samples;
 545    } else {
 546       min_array_element = irb->mt_layer;
 547    }
 548
 549    surf[0] = surftype << BRW_SURFACE_TYPE_SHIFT |
 550              format << BRW_SURFACE_FORMAT_SHIFT |
 551              (irb->mt->array_spacing_lod0 ? GEN7_SURFACE_ARYSPC_LOD0
 552                                           : GEN7_SURFACE_ARYSPC_FULL) |
 553              gen7_surface_tiling_mode(region->tiling);
 554
 555    if (irb->mt->align_h == 4)
 556       surf[0] |= GEN7_SURFACE_VALIGN_4;
 557    if (irb->mt->align_w == 8)
 558       surf[0] |= GEN7_SURFACE_HALIGN_8;
 559
 560    if (is_array) {
 561       surf[0] |= GEN7_SURFACE_IS_ARRAY;
 562    }
 563
 564    surf[1] = region->bo->offset;
 565
 566    assert(brw->has_surface_tile_offset);
 567
 568    surf[5] = SET_FIELD(mocs, GEN7_SURFACE_MOCS) |
 569              (irb->mt_level - irb->mt->first_level);
 570
 571    surf[2] = SET_FIELD(irb->mt->logical_width0 - 1, GEN7_SURFACE_WIDTH) |
 572              SET_FIELD(irb->mt->logical_height0 - 1, GEN7_SURFACE_HEIGHT);
 573
 574    surf[3] = ((depth - 1) << BRW_SURFACE_DEPTH_SHIFT) |
 575              (region->pitch - 1);
 576
 577    surf[4] = gen7_surface_msaa_bits(irb->mt->num_samples, irb->mt->msaa_layout) |
 578              min_array_element << GEN7_SURFACE_MIN_ARRAY_ELEMENT_SHIFT |
 579              (depth - 1) << GEN7_SURFACE_RENDER_TARGET_VIEW_EXTENT_SHIFT;
 580
 581    if (irb->mt->mcs_mt) {
 582       gen7_set_surface_mcs_info(brw, surf, brw->wm.base.surf_offset[surf_index],
 583                                 irb->mt->mcs_mt, true /* is RT */);
 584    }
 585
 586    surf[7] = irb->mt->fast_clear_color_value;
 587
 588    if (brw->is_haswell) {
 589       surf[7] |= (SET_FIELD(HSW_SCS_RED,   GEN7_SURFACE_SCS_R) |
 590                   SET_FIELD(HSW_SCS_GREEN, GEN7_SURFACE_SCS_G) |
 591                   SET_FIELD(HSW_SCS_BLUE,  GEN7_SURFACE_SCS_B) |
 592                   SET_FIELD(HSW_SCS_ALPHA, GEN7_SURFACE_SCS_A));
 593    }
 594
 595    drm_intel_bo_emit_reloc(brw->batch.bo,
 596                            brw->wm.base.surf_offset[surf_index] + 4,
 597                            region->bo,
 598                            surf[1] - region->bo->offset,
 599                            I915_GEM_DOMAIN_RENDER,
 600                            I915_GEM_DOMAIN_RENDER);
 601
 602    gen7_check_surface_setup(surf, true /* is_render_target */);
 603 }
 604
 605 void
 606 gen7_init_vtable_surface_functions(struct brw_context *brw)
 607 {
 608    brw->vtbl.update_texture_surface = gen7_update_texture_surface;
 609    brw->vtbl.update_renderbuffer_surface = gen7_update_renderbuffer_surface;
 610    brw->vtbl.update_null_renderbuffer_surface =
 611       gen7_update_null_renderbuffer_surface;
 612    brw->vtbl.create_constant_surface = gen7_create_constant_surface;
 613 }