2 * Copyright © 2011 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
23 #include "main/mtypes.h"
24 #include "main/blend.h"
25 #include "main/samplerobj.h"
26 #include "main/texformat.h"
27 #include "program/prog_parameter.h"
29 #include "intel_mipmap_tree.h"
30 #include "intel_batchbuffer.h"
31 #include "intel_tex.h"
32 #include "intel_fbo.h"
33 #include "intel_buffer_objects.h"
35 #include "brw_context.h"
36 #include "brw_state.h"
37 #include "brw_defines.h"
41 * Convert an swizzle enumeration (i.e. SWIZZLE_X) to one of the Gen7.5+
42 * "Shader Channel Select" enumerations (i.e. HSW_SCS_RED)
45 swizzle_to_scs(GLenum swizzle
, bool need_green_to_blue
)
51 return need_green_to_blue
? HSW_SCS_BLUE
: HSW_SCS_GREEN
;
62 assert(!"Should not get here: invalid swizzle mode");
67 gen7_surface_tiling_mode(uint32_t tiling
)
71 return GEN7_SURFACE_TILING_X
;
73 return GEN7_SURFACE_TILING_Y
;
75 return GEN7_SURFACE_TILING_NONE
;
81 gen7_surface_msaa_bits(unsigned num_samples
, enum intel_msaa_layout layout
)
86 ss4
|= GEN7_SURFACE_MULTISAMPLECOUNT_8
;
87 else if (num_samples
> 1)
88 ss4
|= GEN7_SURFACE_MULTISAMPLECOUNT_4
;
90 ss4
|= GEN7_SURFACE_MULTISAMPLECOUNT_1
;
92 if (layout
== INTEL_MSAA_LAYOUT_IMS
)
93 ss4
|= GEN7_SURFACE_MSFMT_DEPTH_STENCIL
;
95 ss4
|= GEN7_SURFACE_MSFMT_MSS
;
102 gen7_set_surface_mcs_info(struct brw_context
*brw
,
104 uint32_t surf_offset
,
105 const struct intel_mipmap_tree
*mcs_mt
,
106 bool is_render_target
)
108 /* From the Ivy Bridge PRM, Vol4 Part1 p76, "MCS Base Address":
110 * "The MCS surface must be stored as Tile Y."
112 assert(mcs_mt
->region
->tiling
== I915_TILING_Y
);
114 /* Compute the pitch in units of tiles. To do this we need to divide the
115 * pitch in bytes by 128, since a single Y-tile is 128 bytes wide.
117 unsigned pitch_tiles
= mcs_mt
->region
->pitch
/ 128;
119 /* The upper 20 bits of surface state DWORD 6 are the upper 20 bits of the
120 * GPU address of the MCS buffer; the lower 12 bits contain other control
121 * information. Since buffer addresses are always on 4k boundaries (and
122 * thus have their lower 12 bits zero), we can use an ordinary reloc to do
123 * the necessary address translation.
125 assert ((mcs_mt
->region
->bo
->offset
& 0xfff) == 0);
127 surf
[6] = GEN7_SURFACE_MCS_ENABLE
|
128 SET_FIELD(pitch_tiles
- 1, GEN7_SURFACE_MCS_PITCH
) |
129 mcs_mt
->region
->bo
->offset
;
131 drm_intel_bo_emit_reloc(brw
->batch
.bo
,
135 is_render_target
? I915_GEM_DOMAIN_RENDER
136 : I915_GEM_DOMAIN_SAMPLER
,
137 is_render_target
? I915_GEM_DOMAIN_RENDER
: 0);
142 gen7_check_surface_setup(uint32_t *surf
, bool is_render_target
)
144 unsigned num_multisamples
= surf
[4] & INTEL_MASK(5, 3);
145 unsigned multisampled_surface_storage_format
= surf
[4] & (1 << 6);
146 unsigned surface_array_spacing
= surf
[0] & (1 << 10);
147 bool is_multisampled
= num_multisamples
!= GEN7_SURFACE_MULTISAMPLECOUNT_1
;
149 (void) surface_array_spacing
;
151 /* From the Ivybridge PRM, Volume 4 Part 1, page 66 (RENDER_SURFACE_STATE
152 * dword 0 bit 10 "Surface Array Spacing" Programming Notes):
154 * If Multisampled Surface Storage Format is MSFMT_MSS and Number of
155 * Multisamples is not MULTISAMPLECOUNT_1, this field must be set to
158 if (multisampled_surface_storage_format
== GEN7_SURFACE_MSFMT_MSS
160 assert(surface_array_spacing
== GEN7_SURFACE_ARYSPC_LOD0
);
162 /* From the Ivybridge PRM, Volume 4 Part 1, page 72 (RENDER_SURFACE_STATE
163 * dword 4 bit 6 "Multisampled Surface Storage" Programming Notes):
165 * All multisampled render target surfaces must have this field set to
170 * This field is ignored if Number of Multisamples is MULTISAMPLECOUNT_1.
172 if (is_render_target
&& is_multisampled
) {
173 assert(multisampled_surface_storage_format
== GEN7_SURFACE_MSFMT_MSS
);
176 /* From the Ivybridge PRM, Volume 4 Part 1, page 72 (RENDER_SURFACE_STATE
177 * dword 4 bit 6 "Multisampled Surface Storage Format" Errata):
179 * If the surface’s Number of Multisamples is MULTISAMPLECOUNT_8, Width
180 * is >= 8192 (meaning the actual surface width is >= 8193 pixels), this
181 * field must be set to MSFMT_MSS.
183 uint32_t width
= GET_FIELD(surf
[2], GEN7_SURFACE_WIDTH
) + 1;
184 if (num_multisamples
== GEN7_SURFACE_MULTISAMPLECOUNT_8
&& width
>= 8193) {
185 assert(multisampled_surface_storage_format
== GEN7_SURFACE_MSFMT_MSS
);
188 /* From the Ivybridge PRM, Volume 4 Part 1, page 72 (RENDER_SURFACE_STATE
189 * dword 4 bit 6 "Multisampled Surface Storage Format" Errata):
191 * If the surface’s Number of Multisamples is MULTISAMPLECOUNT_8,
192 * ((Depth+1) * (Height+1)) is > 4,194,304, OR if the surface’s Number of
193 * Multisamples is MULTISAMPLECOUNT_4, ((Depth+1) * (Height+1)) is >
194 * 8,388,608, this field must be set to MSFMT_DEPTH_STENCIL.This field
195 * must be set to MSFMT_DEPTH_STENCIL if Surface Format is one of the
196 * following: I24X8_UNORM, L24X8_UNORM, A24X8_UNORM, or
197 * R24_UNORM_X8_TYPELESS.
199 * But also (from the Programming Notes):
201 * This field is ignored if Number of Multisamples is MULTISAMPLECOUNT_1.
203 uint32_t depth
= GET_FIELD(surf
[3], BRW_SURFACE_DEPTH
) + 1;
204 uint32_t height
= GET_FIELD(surf
[2], GEN7_SURFACE_HEIGHT
) + 1;
205 if (num_multisamples
== GEN7_SURFACE_MULTISAMPLECOUNT_8
&&
206 depth
* height
> 4194304) {
207 assert(multisampled_surface_storage_format
==
208 GEN7_SURFACE_MSFMT_DEPTH_STENCIL
);
210 if (num_multisamples
== GEN7_SURFACE_MULTISAMPLECOUNT_4
&&
211 depth
* height
> 8388608) {
212 assert(multisampled_surface_storage_format
==
213 GEN7_SURFACE_MSFMT_DEPTH_STENCIL
);
215 if (is_multisampled
) {
216 switch (GET_FIELD(surf
[0], BRW_SURFACE_FORMAT
)) {
217 case BRW_SURFACEFORMAT_I24X8_UNORM
:
218 case BRW_SURFACEFORMAT_L24X8_UNORM
:
219 case BRW_SURFACEFORMAT_A24X8_UNORM
:
220 case BRW_SURFACEFORMAT_R24_UNORM_X8_TYPELESS
:
221 assert(multisampled_surface_storage_format
==
222 GEN7_SURFACE_MSFMT_DEPTH_STENCIL
);
228 gen7_emit_buffer_surface_state(struct brw_context
*brw
,
229 uint32_t *out_offset
,
231 unsigned buffer_offset
,
232 unsigned surface_format
,
233 unsigned buffer_size
,
237 uint32_t *surf
= brw_state_batch(brw
, AUB_TRACE_SURFACE_STATE
,
238 8 * 4, 32, out_offset
);
239 memset(surf
, 0, 8 * 4);
241 surf
[0] = BRW_SURFACE_BUFFER
<< BRW_SURFACE_TYPE_SHIFT
|
242 surface_format
<< BRW_SURFACE_FORMAT_SHIFT
|
243 BRW_SURFACE_RC_READ_WRITE
;
244 surf
[1] = (bo
? bo
->offset
: 0) + buffer_offset
; /* reloc */
245 surf
[2] = SET_FIELD((buffer_size
- 1) & 0x7f, GEN7_SURFACE_WIDTH
) |
246 SET_FIELD(((buffer_size
- 1) >> 7) & 0x3fff, GEN7_SURFACE_HEIGHT
);
247 surf
[3] = SET_FIELD(((buffer_size
- 1) >> 21) & 0x3f, BRW_SURFACE_DEPTH
) |
250 surf
[5] = SET_FIELD(mocs
, GEN7_SURFACE_MOCS
);
252 if (brw
->is_haswell
) {
253 surf
[7] |= (SET_FIELD(HSW_SCS_RED
, GEN7_SURFACE_SCS_R
) |
254 SET_FIELD(HSW_SCS_GREEN
, GEN7_SURFACE_SCS_G
) |
255 SET_FIELD(HSW_SCS_BLUE
, GEN7_SURFACE_SCS_B
) |
256 SET_FIELD(HSW_SCS_ALPHA
, GEN7_SURFACE_SCS_A
));
259 /* Emit relocation to surface contents */
261 drm_intel_bo_emit_reloc(brw
->batch
.bo
, *out_offset
+ 4,
262 bo
, buffer_offset
, I915_GEM_DOMAIN_SAMPLER
, 0);
265 gen7_check_surface_setup(surf
, false /* is_render_target */);
269 gen7_update_buffer_texture_surface(struct gl_context
*ctx
,
271 uint32_t *surf_offset
)
273 struct brw_context
*brw
= brw_context(ctx
);
274 struct gl_texture_object
*tObj
= ctx
->Texture
.Unit
[unit
]._Current
;
275 struct intel_buffer_object
*intel_obj
=
276 intel_buffer_object(tObj
->BufferObject
);
277 drm_intel_bo
*bo
= intel_obj
? intel_obj
->buffer
: NULL
;
278 gl_format format
= tObj
->_BufferObjectFormat
;
280 uint32_t surface_format
= brw_format_for_mesa_format(format
);
281 if (surface_format
== 0 && format
!= MESA_FORMAT_RGBA_FLOAT32
) {
282 _mesa_problem(NULL
, "bad format %s for texture buffer\n",
283 _mesa_get_format_name(format
));
286 int texel_size
= _mesa_get_format_bytes(format
);
287 int w
= intel_obj
? intel_obj
->Base
.Size
/ texel_size
: 0;
289 gen7_emit_buffer_surface_state(brw
,
300 gen7_update_texture_surface(struct gl_context
*ctx
,
302 uint32_t *surf_offset
,
305 struct brw_context
*brw
= brw_context(ctx
);
306 struct gl_texture_object
*tObj
= ctx
->Texture
.Unit
[unit
]._Current
;
307 struct intel_texture_object
*intelObj
= intel_texture_object(tObj
);
308 struct intel_mipmap_tree
*mt
= intelObj
->mt
;
309 struct gl_texture_image
*firstImage
= tObj
->Image
[0][tObj
->BaseLevel
];
310 struct gl_sampler_object
*sampler
= _mesa_get_samplerobj(ctx
, unit
);
312 if (tObj
->Target
== GL_TEXTURE_BUFFER
) {
313 gen7_update_buffer_texture_surface(ctx
, unit
, surf_offset
);
317 uint32_t *surf
= brw_state_batch(brw
, AUB_TRACE_SURFACE_STATE
,
318 8 * 4, 32, surf_offset
);
319 memset(surf
, 0, 8 * 4);
321 uint32_t tex_format
= translate_tex_format(brw
,
324 sampler
->sRGBDecode
);
326 if (for_gather
&& tex_format
== BRW_SURFACEFORMAT_R32G32_FLOAT
)
327 tex_format
= BRW_SURFACEFORMAT_R32G32_FLOAT_LD
;
329 surf
[0] = translate_tex_target(tObj
->Target
) << BRW_SURFACE_TYPE_SHIFT
|
330 tex_format
<< BRW_SURFACE_FORMAT_SHIFT
|
331 gen7_surface_tiling_mode(mt
->region
->tiling
) |
332 BRW_SURFACE_CUBEFACE_ENABLES
;
334 if (mt
->align_h
== 4)
335 surf
[0] |= GEN7_SURFACE_VALIGN_4
;
336 if (mt
->align_w
== 8)
337 surf
[0] |= GEN7_SURFACE_HALIGN_8
;
339 if (mt
->logical_depth0
> 1 && tObj
->Target
!= GL_TEXTURE_3D
)
340 surf
[0] |= GEN7_SURFACE_IS_ARRAY
;
342 if (mt
->array_spacing_lod0
)
343 surf
[0] |= GEN7_SURFACE_ARYSPC_LOD0
;
345 surf
[1] = mt
->region
->bo
->offset
+ mt
->offset
; /* reloc */
347 surf
[2] = SET_FIELD(mt
->logical_width0
- 1, GEN7_SURFACE_WIDTH
) |
348 SET_FIELD(mt
->logical_height0
- 1, GEN7_SURFACE_HEIGHT
);
349 surf
[3] = SET_FIELD(mt
->logical_depth0
- 1, BRW_SURFACE_DEPTH
) |
350 ((intelObj
->mt
->region
->pitch
) - 1);
352 surf
[4] = gen7_surface_msaa_bits(mt
->num_samples
, mt
->msaa_layout
);
354 surf
[5] = (SET_FIELD(GEN7_MOCS_L3
, GEN7_SURFACE_MOCS
) |
355 SET_FIELD(tObj
->BaseLevel
- mt
->first_level
,
356 GEN7_SURFACE_MIN_LOD
) |
358 (intelObj
->_MaxLevel
- tObj
->BaseLevel
));
360 if (brw
->is_haswell
) {
361 /* Handling GL_ALPHA as a surface format override breaks 1.30+ style
362 * texturing functions that return a float, as our code generation always
363 * selects the .x channel (which would always be 0).
365 const bool alpha_depth
= tObj
->DepthMode
== GL_ALPHA
&&
366 (firstImage
->_BaseFormat
== GL_DEPTH_COMPONENT
||
367 firstImage
->_BaseFormat
== GL_DEPTH_STENCIL
);
369 const int swizzle
= unlikely(alpha_depth
)
370 ? SWIZZLE_XYZW
: brw_get_texture_swizzle(ctx
, tObj
);
372 const bool need_scs_green_to_blue
= for_gather
&& tex_format
== BRW_SURFACEFORMAT_R32G32_FLOAT_LD
;
375 SET_FIELD(swizzle_to_scs(GET_SWZ(swizzle
, 0), need_scs_green_to_blue
), GEN7_SURFACE_SCS_R
) |
376 SET_FIELD(swizzle_to_scs(GET_SWZ(swizzle
, 1), need_scs_green_to_blue
), GEN7_SURFACE_SCS_G
) |
377 SET_FIELD(swizzle_to_scs(GET_SWZ(swizzle
, 2), need_scs_green_to_blue
), GEN7_SURFACE_SCS_B
) |
378 SET_FIELD(swizzle_to_scs(GET_SWZ(swizzle
, 3), need_scs_green_to_blue
), GEN7_SURFACE_SCS_A
);
381 /* Emit relocation to surface contents */
382 drm_intel_bo_emit_reloc(brw
->batch
.bo
,
384 intelObj
->mt
->region
->bo
,
385 surf
[1] - intelObj
->mt
->region
->bo
->offset
,
386 I915_GEM_DOMAIN_SAMPLER
, 0);
388 gen7_check_surface_setup(surf
, false /* is_render_target */);
392 * Create the constant buffer surface. Vertex/fragment shader constants will
393 * be read from this buffer with Data Port Read instructions/messages.
396 gen7_create_constant_surface(struct brw_context
*brw
,
400 uint32_t *out_offset
,
403 uint32_t stride
= dword_pitch
? 4 : 16;
404 uint32_t elements
= ALIGN(size
, stride
) / stride
;
406 gen7_emit_buffer_surface_state(brw
,
410 BRW_SURFACEFORMAT_R32G32B32A32_FLOAT
,
417 * Create a surface for shader time.
420 gen7_create_shader_time_surface(struct brw_context
*brw
, uint32_t *out_offset
)
422 gen7_emit_buffer_surface_state(brw
,
426 BRW_SURFACEFORMAT_RAW
,
427 brw
->shader_time
.bo
->size
,
433 gen7_update_null_renderbuffer_surface(struct brw_context
*brw
, unsigned unit
)
435 /* From the Ivy bridge PRM, Vol4 Part1 p62 (Surface Type: Programming
438 * A null surface is used in instances where an actual surface is not
439 * bound. When a write message is generated to a null surface, no
440 * actual surface is written to. When a read message (including any
441 * sampling engine message) is generated to a null surface, the result
442 * is all zeros. Note that a null surface type is allowed to be used
443 * with all messages, even if it is not specificially indicated as
444 * supported. All of the remaining fields in surface state are ignored
445 * for null surfaces, with the following exceptions: Width, Height,
446 * Depth, LOD, and Render Target View Extent fields must match the
447 * depth buffer’s corresponding state for all render target surfaces,
450 struct gl_context
*ctx
= &brw
->ctx
;
453 const struct gl_framebuffer
*fb
= ctx
->DrawBuffer
;
455 uint32_t *surf
= brw_state_batch(brw
, AUB_TRACE_SURFACE_STATE
, 8 * 4, 32,
456 &brw
->wm
.base
.surf_offset
[SURF_INDEX_DRAW(unit
)]);
457 memset(surf
, 0, 8 * 4);
459 /* From the Ivybridge PRM, Volume 4, Part 1, page 65,
460 * Tiled Surface: Programming Notes:
461 * "If Surface Type is SURFTYPE_NULL, this field must be TRUE."
463 surf
[0] = BRW_SURFACE_NULL
<< BRW_SURFACE_TYPE_SHIFT
|
464 BRW_SURFACEFORMAT_B8G8R8A8_UNORM
<< BRW_SURFACE_FORMAT_SHIFT
|
465 GEN7_SURFACE_TILING_Y
;
467 surf
[2] = SET_FIELD(fb
->Width
- 1, GEN7_SURFACE_WIDTH
) |
468 SET_FIELD(fb
->Height
- 1, GEN7_SURFACE_HEIGHT
);
470 gen7_check_surface_setup(surf
, true /* is_render_target */);
474 * Sets up a surface state structure to point at the given region.
475 * While it is only used for the front/back buffer currently, it should be
476 * usable for further buffers when doing ARB_draw_buffer support.
479 gen7_update_renderbuffer_surface(struct brw_context
*brw
,
480 struct gl_renderbuffer
*rb
,
484 struct gl_context
*ctx
= &brw
->ctx
;
485 struct intel_renderbuffer
*irb
= intel_renderbuffer(rb
);
486 struct intel_region
*region
= irb
->mt
->region
;
489 gl_format rb_format
= _mesa_get_render_format(ctx
, intel_rb_format(irb
));
491 bool is_array
= false;
492 int depth
= MAX2(rb
->Depth
, 1);
493 int min_array_element
;
494 const uint8_t mocs
= GEN7_MOCS_L3
;
495 GLenum gl_target
= rb
->TexImage
?
496 rb
->TexImage
->TexObject
->Target
: GL_TEXTURE_2D
;
498 uint32_t surf_index
= SURF_INDEX_DRAW(unit
);
500 uint32_t *surf
= brw_state_batch(brw
, AUB_TRACE_SURFACE_STATE
, 8 * 4, 32,
501 &brw
->wm
.base
.surf_offset
[surf_index
]);
502 memset(surf
, 0, 8 * 4);
504 intel_miptree_used_for_rendering(irb
->mt
);
506 /* Render targets can't use IMS layout */
507 assert(irb
->mt
->msaa_layout
!= INTEL_MSAA_LAYOUT_IMS
);
509 assert(brw_render_target_supported(brw
, rb
));
510 format
= brw
->render_target_format
[rb_format
];
511 if (unlikely(!brw
->format_supported_as_render_target
[rb_format
])) {
512 _mesa_problem(ctx
, "%s: renderbuffer format %s unsupported\n",
513 __FUNCTION__
, _mesa_get_format_name(rb_format
));
517 case GL_TEXTURE_CUBE_MAP_ARRAY
:
518 case GL_TEXTURE_CUBE_MAP
:
519 surftype
= BRW_SURFACE_2D
;
524 surftype
= translate_tex_target(gl_target
);
525 is_array
= _mesa_tex_target_is_array(gl_target
);
530 min_array_element
= 0;
531 } else if (irb
->mt
->num_samples
> 1) {
532 min_array_element
= irb
->mt_layer
/ irb
->mt
->num_samples
;
534 min_array_element
= irb
->mt_layer
;
537 surf
[0] = surftype
<< BRW_SURFACE_TYPE_SHIFT
|
538 format
<< BRW_SURFACE_FORMAT_SHIFT
|
539 (irb
->mt
->array_spacing_lod0
? GEN7_SURFACE_ARYSPC_LOD0
540 : GEN7_SURFACE_ARYSPC_FULL
) |
541 gen7_surface_tiling_mode(region
->tiling
);
543 if (irb
->mt
->align_h
== 4)
544 surf
[0] |= GEN7_SURFACE_VALIGN_4
;
545 if (irb
->mt
->align_w
== 8)
546 surf
[0] |= GEN7_SURFACE_HALIGN_8
;
549 surf
[0] |= GEN7_SURFACE_IS_ARRAY
;
552 surf
[1] = region
->bo
->offset
;
554 assert(brw
->has_surface_tile_offset
);
556 surf
[5] = SET_FIELD(mocs
, GEN7_SURFACE_MOCS
) |
557 (irb
->mt_level
- irb
->mt
->first_level
);
559 surf
[2] = SET_FIELD(irb
->mt
->logical_width0
- 1, GEN7_SURFACE_WIDTH
) |
560 SET_FIELD(irb
->mt
->logical_height0
- 1, GEN7_SURFACE_HEIGHT
);
562 surf
[3] = ((depth
- 1) << BRW_SURFACE_DEPTH_SHIFT
) |
565 surf
[4] = gen7_surface_msaa_bits(irb
->mt
->num_samples
, irb
->mt
->msaa_layout
) |
566 min_array_element
<< GEN7_SURFACE_MIN_ARRAY_ELEMENT_SHIFT
|
567 (depth
- 1) << GEN7_SURFACE_RENDER_TARGET_VIEW_EXTENT_SHIFT
;
569 if (irb
->mt
->mcs_mt
) {
570 gen7_set_surface_mcs_info(brw
, surf
, brw
->wm
.base
.surf_offset
[surf_index
],
571 irb
->mt
->mcs_mt
, true /* is RT */);
574 surf
[7] = irb
->mt
->fast_clear_color_value
;
576 if (brw
->is_haswell
) {
577 surf
[7] |= (SET_FIELD(HSW_SCS_RED
, GEN7_SURFACE_SCS_R
) |
578 SET_FIELD(HSW_SCS_GREEN
, GEN7_SURFACE_SCS_G
) |
579 SET_FIELD(HSW_SCS_BLUE
, GEN7_SURFACE_SCS_B
) |
580 SET_FIELD(HSW_SCS_ALPHA
, GEN7_SURFACE_SCS_A
));
583 drm_intel_bo_emit_reloc(brw
->batch
.bo
,
584 brw
->wm
.base
.surf_offset
[surf_index
] + 4,
586 surf
[1] - region
->bo
->offset
,
587 I915_GEM_DOMAIN_RENDER
,
588 I915_GEM_DOMAIN_RENDER
);
590 gen7_check_surface_setup(surf
, true /* is_render_target */);
594 gen7_init_vtable_surface_functions(struct brw_context
*brw
)
596 brw
->vtbl
.update_texture_surface
= gen7_update_texture_surface
;
597 brw
->vtbl
.update_renderbuffer_surface
= gen7_update_renderbuffer_surface
;
598 brw
->vtbl
.update_null_renderbuffer_surface
=
599 gen7_update_null_renderbuffer_surface
;
600 brw
->vtbl
.create_constant_surface
= gen7_create_constant_surface
;