src/mesa/drivers/dri/i965/gen7_wm_surface_state.c

   1 /*
   2  * Copyright © 2011 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23 #include "main/mtypes.h"
  24 #include "main/blend.h"
  25 #include "main/samplerobj.h"
  26 #include "main/texformat.h"
  27 #include "main/teximage.h"
  28 #include "program/prog_parameter.h"
  29 #include "program/prog_instruction.h"
  30
  31 #include "intel_mipmap_tree.h"
  32 #include "intel_batchbuffer.h"
  33 #include "intel_tex.h"
  34 #include "intel_fbo.h"
  35 #include "intel_buffer_objects.h"
  36
  37 #include "brw_context.h"
  38 #include "brw_state.h"
  39 #include "brw_defines.h"
  40 #include "brw_wm.h"
  41
  42 /**
  43  * Convert an swizzle enumeration (i.e. SWIZZLE_X) to one of the Gen7.5+
  44  * "Shader Channel Select" enumerations (i.e. HSW_SCS_RED).  The mappings are
  45  *
  46  * SWIZZLE_X, SWIZZLE_Y, SWIZZLE_Z, SWIZZLE_W, SWIZZLE_ZERO, SWIZZLE_ONE
  47  *         0          1          2          3             4            5
  48  *         4          5          6          7             0            1
  49  *   SCS_RED, SCS_GREEN,  SCS_BLUE, SCS_ALPHA,     SCS_ZERO,     SCS_ONE
  50  *
  51  * which is simply adding 4 then modding by 8 (or anding with 7).
  52  *
  53  * We then may need to apply workarounds for textureGather hardware bugs.
  54  */
  55 static unsigned
  56 swizzle_to_scs(GLenum swizzle, bool need_green_to_blue)
  57 {
  58    unsigned scs = (swizzle + 4) & 7;
  59
  60    return (need_green_to_blue && scs == HSW_SCS_GREEN) ? HSW_SCS_BLUE : scs;
  61 }
  62
  63 uint32_t
  64 gen7_surface_tiling_mode(uint32_t tiling)
  65 {
  66    switch (tiling) {
  67    case I915_TILING_X:
  68       return GEN7_SURFACE_TILING_X;
  69    case I915_TILING_Y:
  70       return GEN7_SURFACE_TILING_Y;
  71    default:
  72       return GEN7_SURFACE_TILING_NONE;
  73    }
  74 }
  75
  76
  77 uint32_t
  78 gen7_surface_msaa_bits(unsigned num_samples, enum intel_msaa_layout layout)
  79 {
  80    uint32_t ss4 = 0;
  81
  82    assert(num_samples <= 16);
  83
  84    /* The SURFACE_MULTISAMPLECOUNT_X enums are simply log2(num_samples) << 3. */
  85    ss4 |= (ffs(MAX2(num_samples, 1)) - 1) << 3;
  86
  87    if (layout == INTEL_MSAA_LAYOUT_IMS)
  88       ss4 |= GEN7_SURFACE_MSFMT_DEPTH_STENCIL;
  89    else
  90       ss4 |= GEN7_SURFACE_MSFMT_MSS;
  91
  92    return ss4;
  93 }
  94
  95
  96 void
  97 gen7_set_surface_mcs_info(struct brw_context *brw,
  98                           uint32_t *surf,
  99                           uint32_t surf_offset,
 100                           const struct intel_mipmap_tree *mcs_mt,
 101                           bool is_render_target)
 102 {
 103    /* From the Ivy Bridge PRM, Vol4 Part1 p76, "MCS Base Address":
 104     *
 105     *     "The MCS surface must be stored as Tile Y."
 106     */
 107    assert(mcs_mt->tiling == I915_TILING_Y);
 108
 109    /* Compute the pitch in units of tiles.  To do this we need to divide the
 110     * pitch in bytes by 128, since a single Y-tile is 128 bytes wide.
 111     */
 112    unsigned pitch_tiles = mcs_mt->pitch / 128;
 113
 114    /* The upper 20 bits of surface state DWORD 6 are the upper 20 bits of the
 115     * GPU address of the MCS buffer; the lower 12 bits contain other control
 116     * information.  Since buffer addresses are always on 4k boundaries (and
 117     * thus have their lower 12 bits zero), we can use an ordinary reloc to do
 118     * the necessary address translation.
 119     */
 120    assert ((mcs_mt->bo->offset64 & 0xfff) == 0);
 121
 122    surf[6] = GEN7_SURFACE_MCS_ENABLE |
 123              SET_FIELD(pitch_tiles - 1, GEN7_SURFACE_MCS_PITCH) |
 124              mcs_mt->bo->offset64;
 125
 126    drm_intel_bo_emit_reloc(brw->batch.bo,
 127                            surf_offset + 6 * 4,
 128                            mcs_mt->bo,
 129                            surf[6] & 0xfff,
 130                            is_render_target ? I915_GEM_DOMAIN_RENDER
 131                            : I915_GEM_DOMAIN_SAMPLER,
 132                            is_render_target ? I915_GEM_DOMAIN_RENDER : 0);
 133 }
 134
 135
 136 void
 137 gen7_check_surface_setup(uint32_t *surf, bool is_render_target)
 138 {
 139    unsigned num_multisamples = surf[4] & INTEL_MASK(5, 3);
 140    unsigned multisampled_surface_storage_format = surf[4] & (1 << 6);
 141    unsigned surface_array_spacing = surf[0] & (1 << 10);
 142    bool is_multisampled = num_multisamples != GEN7_SURFACE_MULTISAMPLECOUNT_1;
 143
 144    (void) surface_array_spacing;
 145
 146    /* From the Ivybridge PRM, Volume 4 Part 1, page 66 (RENDER_SURFACE_STATE
 147     * dword 0 bit 10 "Surface Array Spacing" Programming Notes):
 148     *
 149     *   If Multisampled Surface Storage Format is MSFMT_MSS and Number of
 150     *   Multisamples is not MULTISAMPLECOUNT_1, this field must be set to
 151     *   ARYSPC_LOD0.
 152     */
 153    if (multisampled_surface_storage_format == GEN7_SURFACE_MSFMT_MSS
 154        && is_multisampled)
 155       assert(surface_array_spacing == GEN7_SURFACE_ARYSPC_LOD0);
 156
 157    /* From the Ivybridge PRM, Volume 4 Part 1, page 72 (RENDER_SURFACE_STATE
 158     * dword 4 bit 6 "Multisampled Surface Storage" Programming Notes):
 159     *
 160     *   All multisampled render target surfaces must have this field set to
 161     *   MSFMT_MSS.
 162     *
 163     * But also:
 164     *
 165     *   This field is ignored if Number of Multisamples is MULTISAMPLECOUNT_1.
 166     */
 167    if (is_render_target && is_multisampled) {
 168       assert(multisampled_surface_storage_format == GEN7_SURFACE_MSFMT_MSS);
 169    }
 170
 171    /* From the Ivybridge PRM, Volume 4 Part 1, page 72 (RENDER_SURFACE_STATE
 172     * dword 4 bit 6 "Multisampled Surface Storage Format" Errata):
 173     *
 174     *   If the surface’s Number of Multisamples is MULTISAMPLECOUNT_8, Width
 175     *   is >= 8192 (meaning the actual surface width is >= 8193 pixels), this
 176     *   field must be set to MSFMT_MSS.
 177     */
 178    uint32_t width = GET_FIELD(surf[2], GEN7_SURFACE_WIDTH) + 1;
 179    if (num_multisamples == GEN7_SURFACE_MULTISAMPLECOUNT_8 && width >= 8193) {
 180       assert(multisampled_surface_storage_format == GEN7_SURFACE_MSFMT_MSS);
 181    }
 182
 183    /* From the Ivybridge PRM, Volume 4 Part 1, page 72 (RENDER_SURFACE_STATE
 184     * dword 4 bit 6 "Multisampled Surface Storage Format" Errata):
 185     *
 186     *   If the surface’s Number of Multisamples is MULTISAMPLECOUNT_8,
 187     *   ((Depth+1) * (Height+1)) is > 4,194,304, OR if the surface’s Number of
 188     *   Multisamples is MULTISAMPLECOUNT_4, ((Depth+1) * (Height+1)) is >
 189     *   8,388,608, this field must be set to MSFMT_DEPTH_STENCIL.This field
 190     *   must be set to MSFMT_DEPTH_STENCIL if Surface Format is one of the
 191     *   following: I24X8_UNORM, L24X8_UNORM, A24X8_UNORM, or
 192     *   R24_UNORM_X8_TYPELESS.
 193     *
 194     * But also (from the Programming Notes):
 195     *
 196     *   This field is ignored if Number of Multisamples is MULTISAMPLECOUNT_1.
 197     */
 198    uint32_t depth = GET_FIELD(surf[3], BRW_SURFACE_DEPTH) + 1;
 199    uint32_t height = GET_FIELD(surf[2], GEN7_SURFACE_HEIGHT) + 1;
 200    if (num_multisamples == GEN7_SURFACE_MULTISAMPLECOUNT_8 &&
 201        depth * height > 4194304) {
 202       assert(multisampled_surface_storage_format ==
 203              GEN7_SURFACE_MSFMT_DEPTH_STENCIL);
 204    }
 205    if (num_multisamples == GEN7_SURFACE_MULTISAMPLECOUNT_4 &&
 206        depth * height > 8388608) {
 207       assert(multisampled_surface_storage_format ==
 208              GEN7_SURFACE_MSFMT_DEPTH_STENCIL);
 209    }
 210    if (is_multisampled) {
 211       switch (GET_FIELD(surf[0], BRW_SURFACE_FORMAT)) {
 212       case BRW_SURFACEFORMAT_I24X8_UNORM:
 213       case BRW_SURFACEFORMAT_L24X8_UNORM:
 214       case BRW_SURFACEFORMAT_A24X8_UNORM:
 215       case BRW_SURFACEFORMAT_R24_UNORM_X8_TYPELESS:
 216          assert(multisampled_surface_storage_format ==
 217                 GEN7_SURFACE_MSFMT_DEPTH_STENCIL);
 218       }
 219    }
 220 }
 221
 222 static void
 223 gen7_emit_buffer_surface_state(struct brw_context *brw,
 224                                uint32_t *out_offset,
 225                                drm_intel_bo *bo,
 226                                unsigned buffer_offset,
 227                                unsigned surface_format,
 228                                unsigned buffer_size,
 229                                unsigned pitch,
 230                                bool rw)
 231 {
 232    uint32_t *surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE,
 233                                     8 * 4, 32, out_offset);
 234    memset(surf, 0, 8 * 4);
 235
 236    surf[0] = BRW_SURFACE_BUFFER << BRW_SURFACE_TYPE_SHIFT |
 237              surface_format << BRW_SURFACE_FORMAT_SHIFT |
 238              BRW_SURFACE_RC_READ_WRITE;
 239    surf[1] = (bo ? bo->offset64 : 0) + buffer_offset; /* reloc */
 240    surf[2] = SET_FIELD((buffer_size - 1) & 0x7f, GEN7_SURFACE_WIDTH) |
 241              SET_FIELD(((buffer_size - 1) >> 7) & 0x3fff, GEN7_SURFACE_HEIGHT);
 242    if (surface_format == BRW_SURFACEFORMAT_RAW)
 243       surf[3] = SET_FIELD(((buffer_size - 1) >> 21) & 0x3ff, BRW_SURFACE_DEPTH);
 244    else
 245       surf[3] = SET_FIELD(((buffer_size - 1) >> 21) & 0x3f, BRW_SURFACE_DEPTH);
 246    surf[3] |= (pitch - 1);
 247
 248    surf[5] = SET_FIELD(GEN7_MOCS_L3, GEN7_SURFACE_MOCS);
 249
 250    if (brw->is_haswell) {
 251       surf[7] |= (SET_FIELD(HSW_SCS_RED,   GEN7_SURFACE_SCS_R) |
 252                   SET_FIELD(HSW_SCS_GREEN, GEN7_SURFACE_SCS_G) |
 253                   SET_FIELD(HSW_SCS_BLUE,  GEN7_SURFACE_SCS_B) |
 254                   SET_FIELD(HSW_SCS_ALPHA, GEN7_SURFACE_SCS_A));
 255    }
 256
 257    /* Emit relocation to surface contents */
 258    if (bo) {
 259       drm_intel_bo_emit_reloc(brw->batch.bo, *out_offset + 4,
 260                               bo, buffer_offset, I915_GEM_DOMAIN_SAMPLER,
 261                               (rw ? I915_GEM_DOMAIN_SAMPLER : 0));
 262    }
 263
 264    gen7_check_surface_setup(surf, false /* is_render_target */);
 265 }
 266
 267 static void
 268 gen7_emit_texture_surface_state(struct brw_context *brw,
 269                                 struct intel_mipmap_tree *mt,
 270                                 GLenum target,
 271                                 unsigned min_layer, unsigned max_layer,
 272                                 unsigned min_level, unsigned max_level,
 273                                 unsigned format,
 274                                 unsigned swizzle,
 275                                 uint32_t *surf_offset,
 276                                 bool rw, bool for_gather)
 277 {
 278    const unsigned depth = max_layer - min_layer;
 279    uint32_t *surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE,
 280                                     8 * 4, 32, surf_offset);
 281
 282    memset(surf, 0, 8 * 4);
 283
 284    surf[0] = translate_tex_target(target) << BRW_SURFACE_TYPE_SHIFT |
 285              format << BRW_SURFACE_FORMAT_SHIFT |
 286              gen7_surface_tiling_mode(mt->tiling);
 287
 288    /* mask of faces present in cube map; for other surfaces MBZ. */
 289    if (target == GL_TEXTURE_CUBE_MAP || target == GL_TEXTURE_CUBE_MAP_ARRAY)
 290       surf[0] |= BRW_SURFACE_CUBEFACE_ENABLES;
 291
 292    if (mt->valign == 4)
 293       surf[0] |= GEN7_SURFACE_VALIGN_4;
 294    if (mt->halign == 8)
 295       surf[0] |= GEN7_SURFACE_HALIGN_8;
 296
 297    if (_mesa_is_array_texture(target) || target == GL_TEXTURE_CUBE_MAP)
 298       surf[0] |= GEN7_SURFACE_IS_ARRAY;
 299
 300    if (mt->array_layout == ALL_SLICES_AT_EACH_LOD)
 301       surf[0] |= GEN7_SURFACE_ARYSPC_LOD0;
 302
 303    surf[1] = mt->bo->offset64 + mt->offset; /* reloc */
 304
 305    surf[2] = SET_FIELD(mt->logical_width0 - 1, GEN7_SURFACE_WIDTH) |
 306              SET_FIELD(mt->logical_height0 - 1, GEN7_SURFACE_HEIGHT);
 307
 308    surf[3] = SET_FIELD(depth - 1, BRW_SURFACE_DEPTH) |
 309              (mt->pitch - 1);
 310
 311    if (brw->is_haswell && _mesa_is_format_integer(mt->format))
 312       surf[3] |= HSW_SURFACE_IS_INTEGER_FORMAT;
 313
 314    surf[4] = gen7_surface_msaa_bits(mt->num_samples, mt->msaa_layout) |
 315              SET_FIELD(min_layer, GEN7_SURFACE_MIN_ARRAY_ELEMENT) |
 316              SET_FIELD(depth - 1, GEN7_SURFACE_RENDER_TARGET_VIEW_EXTENT);
 317
 318    surf[5] = (SET_FIELD(GEN7_MOCS_L3, GEN7_SURFACE_MOCS) |
 319               SET_FIELD(min_level - mt->first_level, GEN7_SURFACE_MIN_LOD) |
 320               /* mip count */
 321               (max_level - min_level - 1));
 322
 323    surf[7] = mt->fast_clear_color_value;
 324
 325    if (brw->is_haswell) {
 326       const bool need_scs_green_to_blue = for_gather && format == BRW_SURFACEFORMAT_R32G32_FLOAT_LD;
 327
 328       surf[7] |=
 329          SET_FIELD(swizzle_to_scs(GET_SWZ(swizzle, 0), need_scs_green_to_blue), GEN7_SURFACE_SCS_R) |
 330          SET_FIELD(swizzle_to_scs(GET_SWZ(swizzle, 1), need_scs_green_to_blue), GEN7_SURFACE_SCS_G) |
 331          SET_FIELD(swizzle_to_scs(GET_SWZ(swizzle, 2), need_scs_green_to_blue), GEN7_SURFACE_SCS_B) |
 332          SET_FIELD(swizzle_to_scs(GET_SWZ(swizzle, 3), need_scs_green_to_blue), GEN7_SURFACE_SCS_A);
 333    }
 334
 335    if (mt->mcs_mt) {
 336       gen7_set_surface_mcs_info(brw, surf, *surf_offset,
 337                                 mt->mcs_mt, false /* is RT */);
 338    }
 339
 340    /* Emit relocation to surface contents */
 341    drm_intel_bo_emit_reloc(brw->batch.bo,
 342                            *surf_offset + 4,
 343                            mt->bo,
 344                            surf[1] - mt->bo->offset64,
 345                            I915_GEM_DOMAIN_SAMPLER,
 346                            (rw ? I915_GEM_DOMAIN_SAMPLER : 0));
 347
 348    gen7_check_surface_setup(surf, false /* is_render_target */);
 349 }
 350
 351 static void
 352 gen7_update_texture_surface(struct gl_context *ctx,
 353                             unsigned unit,
 354                             uint32_t *surf_offset,
 355                             bool for_gather)
 356 {
 357    struct brw_context *brw = brw_context(ctx);
 358    struct gl_texture_object *obj = ctx->Texture.Unit[unit]._Current;
 359
 360    if (obj->Target == GL_TEXTURE_BUFFER) {
 361       brw_update_buffer_texture_surface(ctx, unit, surf_offset);
 362
 363    } else {
 364       struct intel_texture_object *intel_obj = intel_texture_object(obj);
 365       struct intel_mipmap_tree *mt = intel_obj->mt;
 366       struct gl_sampler_object *sampler = _mesa_get_samplerobj(ctx, unit);
 367       /* If this is a view with restricted NumLayers, then our effective depth
 368        * is not just the miptree depth.
 369        */
 370       const unsigned depth = (obj->Immutable && obj->Target != GL_TEXTURE_3D ?
 371                               obj->NumLayers : mt->logical_depth0);
 372
 373       /* Handling GL_ALPHA as a surface format override breaks 1.30+ style
 374        * texturing functions that return a float, as our code generation always
 375        * selects the .x channel (which would always be 0).
 376        */
 377       struct gl_texture_image *firstImage = obj->Image[0][obj->BaseLevel];
 378       const bool alpha_depth = obj->DepthMode == GL_ALPHA &&
 379          (firstImage->_BaseFormat == GL_DEPTH_COMPONENT ||
 380           firstImage->_BaseFormat == GL_DEPTH_STENCIL);
 381       const unsigned swizzle = (unlikely(alpha_depth) ? SWIZZLE_XYZW :
 382                                 brw_get_texture_swizzle(&brw->ctx, obj));
 383
 384       unsigned format = translate_tex_format(
 385          brw, intel_obj->_Format, sampler->sRGBDecode);
 386
 387       if (for_gather && format == BRW_SURFACEFORMAT_R32G32_FLOAT)
 388          format = BRW_SURFACEFORMAT_R32G32_FLOAT_LD;
 389
 390       gen7_emit_texture_surface_state(brw, mt, obj->Target,
 391                                       obj->MinLayer, obj->MinLayer + depth,
 392                                       obj->MinLevel + obj->BaseLevel,
 393                                       obj->MinLevel + intel_obj->_MaxLevel + 1,
 394                                       format, swizzle,
 395                                       surf_offset, false, for_gather);
 396    }
 397 }
 398
 399 /**
 400  * Creates a null surface.
 401  *
 402  * This is used when the shader doesn't write to any color output.  An FB
 403  * write to target 0 will still be emitted, because that's how the thread is
 404  * terminated (and computed depth is returned), so we need to have the
 405  * hardware discard the target 0 color output..
 406  */
 407 static void
 408 gen7_emit_null_surface_state(struct brw_context *brw,
 409                              unsigned width,
 410                              unsigned height,
 411                              unsigned samples,
 412                              uint32_t *out_offset)
 413 {
 414    /* From the Ivy bridge PRM, Vol4 Part1 p62 (Surface Type: Programming
 415     * Notes):
 416     *
 417     *     A null surface is used in instances where an actual surface is not
 418     *     bound. When a write message is generated to a null surface, no
 419     *     actual surface is written to. When a read message (including any
 420     *     sampling engine message) is generated to a null surface, the result
 421     *     is all zeros. Note that a null surface type is allowed to be used
 422     *     with all messages, even if it is not specificially indicated as
 423     *     supported. All of the remaining fields in surface state are ignored
 424     *     for null surfaces, with the following exceptions: Width, Height,
 425     *     Depth, LOD, and Render Target View Extent fields must match the
 426     *     depth buffer’s corresponding state for all render target surfaces,
 427     *     including null.
 428     */
 429    uint32_t *surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE, 8 * 4, 32,
 430                                     out_offset);
 431    memset(surf, 0, 8 * 4);
 432
 433    /* From the Ivybridge PRM, Volume 4, Part 1, page 65,
 434     * Tiled Surface: Programming Notes:
 435     * "If Surface Type is SURFTYPE_NULL, this field must be TRUE."
 436     */
 437    surf[0] = BRW_SURFACE_NULL << BRW_SURFACE_TYPE_SHIFT |
 438              BRW_SURFACEFORMAT_B8G8R8A8_UNORM << BRW_SURFACE_FORMAT_SHIFT |
 439              GEN7_SURFACE_TILING_Y;
 440
 441    surf[2] = SET_FIELD(width - 1, GEN7_SURFACE_WIDTH) |
 442              SET_FIELD(height - 1, GEN7_SURFACE_HEIGHT);
 443
 444    gen7_check_surface_setup(surf, true /* is_render_target */);
 445 }
 446
 447 /**
 448  * Sets up a surface state structure to point at the given region.
 449  * While it is only used for the front/back buffer currently, it should be
 450  * usable for further buffers when doing ARB_draw_buffer support.
 451  */
 452 static uint32_t
 453 gen7_update_renderbuffer_surface(struct brw_context *brw,
 454                                  struct gl_renderbuffer *rb,
 455                                  bool layered, unsigned unit /* unused */,
 456                                  uint32_t surf_index)
 457 {
 458    struct gl_context *ctx = &brw->ctx;
 459    struct intel_renderbuffer *irb = intel_renderbuffer(rb);
 460    struct intel_mipmap_tree *mt = irb->mt;
 461    uint32_t format;
 462    /* _NEW_BUFFERS */
 463    mesa_format rb_format = _mesa_get_render_format(ctx, intel_rb_format(irb));
 464    uint32_t surftype;
 465    bool is_array = false;
 466    int depth = MAX2(irb->layer_count, 1);
 467    const uint8_t mocs = GEN7_MOCS_L3;
 468    uint32_t offset;
 469
 470    int min_array_element = irb->mt_layer / MAX2(mt->num_samples, 1);
 471
 472    GLenum gl_target = rb->TexImage ?
 473                          rb->TexImage->TexObject->Target : GL_TEXTURE_2D;
 474
 475    uint32_t *surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE, 8 * 4, 32,
 476                                     &offset);
 477    memset(surf, 0, 8 * 4);
 478
 479    intel_miptree_used_for_rendering(irb->mt);
 480
 481    /* Render targets can't use IMS layout */
 482    assert(irb->mt->msaa_layout != INTEL_MSAA_LAYOUT_IMS);
 483
 484    assert(brw_render_target_supported(brw, rb));
 485    format = brw->render_target_format[rb_format];
 486    if (unlikely(!brw->format_supported_as_render_target[rb_format])) {
 487       _mesa_problem(ctx, "%s: renderbuffer format %s unsupported\n",
 488                     __func__, _mesa_get_format_name(rb_format));
 489    }
 490
 491    switch (gl_target) {
 492    case GL_TEXTURE_CUBE_MAP_ARRAY:
 493    case GL_TEXTURE_CUBE_MAP:
 494       surftype = BRW_SURFACE_2D;
 495       is_array = true;
 496       depth *= 6;
 497       break;
 498    case GL_TEXTURE_3D:
 499       depth = MAX2(irb->mt->logical_depth0, 1);
 500       /* fallthrough */
 501    default:
 502       surftype = translate_tex_target(gl_target);
 503       is_array = _mesa_is_array_texture(gl_target);
 504       break;
 505    }
 506
 507    surf[0] = surftype << BRW_SURFACE_TYPE_SHIFT |
 508              format << BRW_SURFACE_FORMAT_SHIFT |
 509              (irb->mt->array_layout == ALL_SLICES_AT_EACH_LOD ?
 510                  GEN7_SURFACE_ARYSPC_LOD0 : GEN7_SURFACE_ARYSPC_FULL) |
 511              gen7_surface_tiling_mode(mt->tiling);
 512
 513    if (irb->mt->valign == 4)
 514       surf[0] |= GEN7_SURFACE_VALIGN_4;
 515    if (irb->mt->halign == 8)
 516       surf[0] |= GEN7_SURFACE_HALIGN_8;
 517
 518    if (is_array) {
 519       surf[0] |= GEN7_SURFACE_IS_ARRAY;
 520    }
 521
 522    assert(mt->offset % mt->cpp == 0);
 523    surf[1] = mt->bo->offset64 + mt->offset;
 524
 525    assert(brw->has_surface_tile_offset);
 526
 527    surf[5] = SET_FIELD(mocs, GEN7_SURFACE_MOCS) |
 528              (irb->mt_level - irb->mt->first_level);
 529
 530    surf[2] = SET_FIELD(irb->mt->logical_width0 - 1, GEN7_SURFACE_WIDTH) |
 531              SET_FIELD(irb->mt->logical_height0 - 1, GEN7_SURFACE_HEIGHT);
 532
 533    surf[3] = ((depth - 1) << BRW_SURFACE_DEPTH_SHIFT) |
 534              (mt->pitch - 1);
 535
 536    surf[4] = gen7_surface_msaa_bits(irb->mt->num_samples, irb->mt->msaa_layout) |
 537              min_array_element << GEN7_SURFACE_MIN_ARRAY_ELEMENT_SHIFT |
 538              (depth - 1) << GEN7_SURFACE_RENDER_TARGET_VIEW_EXTENT_SHIFT;
 539
 540    if (irb->mt->mcs_mt) {
 541       gen7_set_surface_mcs_info(brw, surf, offset,
 542                                 irb->mt->mcs_mt, true /* is RT */);
 543    }
 544
 545    surf[7] = irb->mt->fast_clear_color_value;
 546
 547    if (brw->is_haswell) {
 548       surf[7] |= (SET_FIELD(HSW_SCS_RED,   GEN7_SURFACE_SCS_R) |
 549                   SET_FIELD(HSW_SCS_GREEN, GEN7_SURFACE_SCS_G) |
 550                   SET_FIELD(HSW_SCS_BLUE,  GEN7_SURFACE_SCS_B) |
 551                   SET_FIELD(HSW_SCS_ALPHA, GEN7_SURFACE_SCS_A));
 552    }
 553
 554    drm_intel_bo_emit_reloc(brw->batch.bo,
 555                            offset + 4,
 556                            mt->bo,
 557                            surf[1] - mt->bo->offset64,
 558                            I915_GEM_DOMAIN_RENDER,
 559                            I915_GEM_DOMAIN_RENDER);
 560
 561    gen7_check_surface_setup(surf, true /* is_render_target */);
 562
 563    return offset;
 564 }
 565
 566 void
 567 gen7_init_vtable_surface_functions(struct brw_context *brw)
 568 {
 569    brw->vtbl.update_texture_surface = gen7_update_texture_surface;
 570    brw->vtbl.update_renderbuffer_surface = gen7_update_renderbuffer_surface;
 571    brw->vtbl.emit_null_surface_state = gen7_emit_null_surface_state;
 572    brw->vtbl.emit_texture_surface_state = gen7_emit_texture_surface_state;
 573    brw->vtbl.emit_buffer_surface_state = gen7_emit_buffer_surface_state;
 574 }