src/mesa/drivers/dri/i965/gen7_wm_surface_state.c

   1 /*
   2  * Copyright © 2011 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23 #include "main/mtypes.h"
  24 #include "main/blend.h"
  25 #include "main/samplerobj.h"
  26 #include "main/texformat.h"
  27 #include "program/prog_parameter.h"
  28
  29 #include "intel_mipmap_tree.h"
  30 #include "intel_batchbuffer.h"
  31 #include "intel_tex.h"
  32 #include "intel_fbo.h"
  33 #include "intel_buffer_objects.h"
  34
  35 #include "brw_context.h"
  36 #include "brw_state.h"
  37 #include "brw_defines.h"
  38 #include "brw_wm.h"
  39
  40 /**
  41  * Convert an swizzle enumeration (i.e. SWIZZLE_X) to one of the Gen7.5+
  42  * "Shader Channel Select" enumerations (i.e. HSW_SCS_RED)
  43  */
  44 static unsigned
  45 swizzle_to_scs(GLenum swizzle)
  46 {
  47    switch (swizzle) {
  48    case SWIZZLE_X:
  49       return HSW_SCS_RED;
  50    case SWIZZLE_Y:
  51       return HSW_SCS_GREEN;
  52    case SWIZZLE_Z:
  53       return HSW_SCS_BLUE;
  54    case SWIZZLE_W:
  55       return HSW_SCS_ALPHA;
  56    case SWIZZLE_ZERO:
  57       return HSW_SCS_ZERO;
  58    case SWIZZLE_ONE:
  59       return HSW_SCS_ONE;
  60    }
  61
  62    assert(!"Should not get here: invalid swizzle mode");
  63    return HSW_SCS_ZERO;
  64 }
  65
  66 uint32_t
  67 gen7_surface_tiling_mode(uint32_t tiling)
  68 {
  69    switch (tiling) {
  70    case I915_TILING_X:
  71       return GEN7_SURFACE_TILING_X;
  72    case I915_TILING_Y:
  73       return GEN7_SURFACE_TILING_Y;
  74    default:
  75       return GEN7_SURFACE_TILING_NONE;
  76    }
  77 }
  78
  79
  80 uint32_t
  81 gen7_surface_msaa_bits(unsigned num_samples, enum intel_msaa_layout layout)
  82 {
  83    uint32_t ss4 = 0;
  84
  85    if (num_samples > 4)
  86       ss4 |= GEN7_SURFACE_MULTISAMPLECOUNT_8;
  87    else if (num_samples > 1)
  88       ss4 |= GEN7_SURFACE_MULTISAMPLECOUNT_4;
  89    else
  90       ss4 |= GEN7_SURFACE_MULTISAMPLECOUNT_1;
  91
  92    if (layout == INTEL_MSAA_LAYOUT_IMS)
  93       ss4 |= GEN7_SURFACE_MSFMT_DEPTH_STENCIL;
  94    else
  95       ss4 |= GEN7_SURFACE_MSFMT_MSS;
  96
  97    return ss4;
  98 }
  99
 100
 101 void
 102 gen7_set_surface_mcs_info(struct brw_context *brw,
 103                           uint32_t *surf,
 104                           uint32_t surf_offset,
 105                           const struct intel_mipmap_tree *mcs_mt,
 106                           bool is_render_target)
 107 {
 108    /* From the Ivy Bridge PRM, Vol4 Part1 p76, "MCS Base Address":
 109     *
 110     *     "The MCS surface must be stored as Tile Y."
 111     */
 112    assert(mcs_mt->region->tiling == I915_TILING_Y);
 113
 114    /* Compute the pitch in units of tiles.  To do this we need to divide the
 115     * pitch in bytes by 128, since a single Y-tile is 128 bytes wide.
 116     */
 117    unsigned pitch_tiles = mcs_mt->region->pitch / 128;
 118
 119    /* The upper 20 bits of surface state DWORD 6 are the upper 20 bits of the
 120     * GPU address of the MCS buffer; the lower 12 bits contain other control
 121     * information.  Since buffer addresses are always on 4k boundaries (and
 122     * thus have their lower 12 bits zero), we can use an ordinary reloc to do
 123     * the necessary address translation.
 124     */
 125    assert ((mcs_mt->region->bo->offset & 0xfff) == 0);
 126
 127    surf[6] = GEN7_SURFACE_MCS_ENABLE |
 128              SET_FIELD(pitch_tiles - 1, GEN7_SURFACE_MCS_PITCH) |
 129              mcs_mt->region->bo->offset;
 130
 131    drm_intel_bo_emit_reloc(brw->batch.bo,
 132                            surf_offset + 6 * 4,
 133                            mcs_mt->region->bo,
 134                            surf[6] & 0xfff,
 135                            is_render_target ? I915_GEM_DOMAIN_RENDER
 136                            : I915_GEM_DOMAIN_SAMPLER,
 137                            is_render_target ? I915_GEM_DOMAIN_RENDER : 0);
 138 }
 139
 140
 141 void
 142 gen7_check_surface_setup(uint32_t *surf, bool is_render_target)
 143 {
 144    unsigned num_multisamples = surf[4] & INTEL_MASK(5, 3);
 145    unsigned multisampled_surface_storage_format = surf[4] & (1 << 6);
 146    unsigned surface_array_spacing = surf[0] & (1 << 10);
 147    bool is_multisampled = num_multisamples != GEN7_SURFACE_MULTISAMPLECOUNT_1;
 148
 149    (void) surface_array_spacing;
 150
 151    /* From the Ivybridge PRM, Volume 4 Part 1, page 66 (RENDER_SURFACE_STATE
 152     * dword 0 bit 10 "Surface Array Spacing" Programming Notes):
 153     *
 154     *   If Multisampled Surface Storage Format is MSFMT_MSS and Number of
 155     *   Multisamples is not MULTISAMPLECOUNT_1, this field must be set to
 156     *   ARYSPC_LOD0.
 157     */
 158    if (multisampled_surface_storage_format == GEN7_SURFACE_MSFMT_MSS
 159        && is_multisampled)
 160       assert(surface_array_spacing == GEN7_SURFACE_ARYSPC_LOD0);
 161
 162    /* From the Ivybridge PRM, Volume 4 Part 1, page 72 (RENDER_SURFACE_STATE
 163     * dword 4 bit 6 "Multisampled Surface Storage" Programming Notes):
 164     *
 165     *   All multisampled render target surfaces must have this field set to
 166     *   MSFMT_MSS.
 167     *
 168     * But also:
 169     *
 170     *   This field is ignored if Number of Multisamples is MULTISAMPLECOUNT_1.
 171     */
 172    if (is_render_target && is_multisampled) {
 173       assert(multisampled_surface_storage_format == GEN7_SURFACE_MSFMT_MSS);
 174    }
 175
 176    /* From the Ivybridge PRM, Volume 4 Part 1, page 72 (RENDER_SURFACE_STATE
 177     * dword 4 bit 6 "Multisampled Surface Storage Format" Errata):
 178     *
 179     *   If the surface’s Number of Multisamples is MULTISAMPLECOUNT_8, Width
 180     *   is >= 8192 (meaning the actual surface width is >= 8193 pixels), this
 181     *   field must be set to MSFMT_MSS.
 182     */
 183    uint32_t width = GET_FIELD(surf[2], GEN7_SURFACE_WIDTH) + 1;
 184    if (num_multisamples == GEN7_SURFACE_MULTISAMPLECOUNT_8 && width >= 8193) {
 185       assert(multisampled_surface_storage_format == GEN7_SURFACE_MSFMT_MSS);
 186    }
 187
 188    /* From the Ivybridge PRM, Volume 4 Part 1, page 72 (RENDER_SURFACE_STATE
 189     * dword 4 bit 6 "Multisampled Surface Storage Format" Errata):
 190     *
 191     *   If the surface’s Number of Multisamples is MULTISAMPLECOUNT_8,
 192     *   ((Depth+1) * (Height+1)) is > 4,194,304, OR if the surface’s Number of
 193     *   Multisamples is MULTISAMPLECOUNT_4, ((Depth+1) * (Height+1)) is >
 194     *   8,388,608, this field must be set to MSFMT_DEPTH_STENCIL.This field
 195     *   must be set to MSFMT_DEPTH_STENCIL if Surface Format is one of the
 196     *   following: I24X8_UNORM, L24X8_UNORM, A24X8_UNORM, or
 197     *   R24_UNORM_X8_TYPELESS.
 198     *
 199     * But also (from the Programming Notes):
 200     *
 201     *   This field is ignored if Number of Multisamples is MULTISAMPLECOUNT_1.
 202     */
 203    uint32_t depth = GET_FIELD(surf[3], BRW_SURFACE_DEPTH) + 1;
 204    uint32_t height = GET_FIELD(surf[2], GEN7_SURFACE_HEIGHT) + 1;
 205    if (num_multisamples == GEN7_SURFACE_MULTISAMPLECOUNT_8 &&
 206        depth * height > 4194304) {
 207       assert(multisampled_surface_storage_format ==
 208              GEN7_SURFACE_MSFMT_DEPTH_STENCIL);
 209    }
 210    if (num_multisamples == GEN7_SURFACE_MULTISAMPLECOUNT_4 &&
 211        depth * height > 8388608) {
 212       assert(multisampled_surface_storage_format ==
 213              GEN7_SURFACE_MSFMT_DEPTH_STENCIL);
 214    }
 215    if (is_multisampled) {
 216       switch (GET_FIELD(surf[0], BRW_SURFACE_FORMAT)) {
 217       case BRW_SURFACEFORMAT_I24X8_UNORM:
 218       case BRW_SURFACEFORMAT_L24X8_UNORM:
 219       case BRW_SURFACEFORMAT_A24X8_UNORM:
 220       case BRW_SURFACEFORMAT_R24_UNORM_X8_TYPELESS:
 221          assert(multisampled_surface_storage_format ==
 222                 GEN7_SURFACE_MSFMT_DEPTH_STENCIL);
 223       }
 224    }
 225 }
 226
 227
 228 static void
 229 gen7_update_buffer_texture_surface(struct gl_context *ctx,
 230                                    unsigned unit,
 231                                    uint32_t *binding_table,
 232                                    unsigned surf_index)
 233 {
 234    struct brw_context *brw = brw_context(ctx);
 235    struct gl_texture_object *tObj = ctx->Texture.Unit[unit]._Current;
 236    struct intel_buffer_object *intel_obj =
 237       intel_buffer_object(tObj->BufferObject);
 238    drm_intel_bo *bo = intel_obj ? intel_obj->buffer : NULL;
 239    gl_format format = tObj->_BufferObjectFormat;
 240
 241    uint32_t *surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE,
 242                                     8 * 4, 32, &binding_table[surf_index]);
 243    memset(surf, 0, 8 * 4);
 244
 245    uint32_t surface_format = brw_format_for_mesa_format(format);
 246    if (surface_format == 0 && format != MESA_FORMAT_RGBA_FLOAT32) {
 247       _mesa_problem(NULL, "bad format %s for texture buffer\n",
 248                     _mesa_get_format_name(format));
 249    }
 250
 251    surf[0] = BRW_SURFACE_BUFFER << BRW_SURFACE_TYPE_SHIFT |
 252              surface_format << BRW_SURFACE_FORMAT_SHIFT |
 253              BRW_SURFACE_RC_READ_WRITE;
 254
 255    if (bo) {
 256       surf[1] = bo->offset; /* reloc */
 257
 258       drm_intel_bo_emit_reloc(brw->batch.bo,
 259                               binding_table[surf_index] + 4,
 260                               bo, 0,
 261                               I915_GEM_DOMAIN_SAMPLER, 0);
 262
 263       int texel_size = _mesa_get_format_bytes(format);
 264       int w = intel_obj->Base.Size / texel_size;
 265
 266       /* note that these differ from GEN6 */
 267       surf[2] = SET_FIELD(w & 0x7f, GEN7_SURFACE_WIDTH) | /* bits 6:0 of size */
 268                 SET_FIELD((w >> 7) & 0x3fff, GEN7_SURFACE_HEIGHT); /* 20:7 */
 269       surf[3] = SET_FIELD((w >> 21) & 0x3f, BRW_SURFACE_DEPTH) | /* bits 26:21 */
 270                 (texel_size - 1);
 271    }
 272
 273    gen7_check_surface_setup(surf, false /* is_render_target */);
 274 }
 275
 276 static void
 277 gen7_update_texture_surface(struct gl_context *ctx,
 278                             unsigned unit,
 279                             uint32_t *binding_table,
 280                             unsigned surf_index)
 281 {
 282    struct brw_context *brw = brw_context(ctx);
 283    struct gl_texture_object *tObj = ctx->Texture.Unit[unit]._Current;
 284    struct intel_texture_object *intelObj = intel_texture_object(tObj);
 285    struct intel_mipmap_tree *mt = intelObj->mt;
 286    struct gl_texture_image *firstImage = tObj->Image[0][tObj->BaseLevel];
 287    struct gl_sampler_object *sampler = _mesa_get_samplerobj(ctx, unit);
 288    uint32_t tile_x, tile_y;
 289
 290    if (tObj->Target == GL_TEXTURE_BUFFER) {
 291       gen7_update_buffer_texture_surface(ctx, unit, binding_table, surf_index);
 292       return;
 293    }
 294
 295    uint32_t *surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE,
 296                                     8 * 4, 32, &binding_table[surf_index]);
 297    memset(surf, 0, 8 * 4);
 298
 299    uint32_t tex_format = translate_tex_format(brw,
 300                                               mt->format,
 301                                               tObj->DepthMode,
 302                                               sampler->sRGBDecode);
 303
 304    surf[0] = translate_tex_target(tObj->Target) << BRW_SURFACE_TYPE_SHIFT |
 305              tex_format << BRW_SURFACE_FORMAT_SHIFT |
 306              gen7_surface_tiling_mode(mt->region->tiling) |
 307              BRW_SURFACE_CUBEFACE_ENABLES;
 308
 309    if (mt->align_h == 4)
 310       surf[0] |= GEN7_SURFACE_VALIGN_4;
 311    if (mt->align_w == 8)
 312       surf[0] |= GEN7_SURFACE_HALIGN_8;
 313
 314    if (mt->logical_depth0 > 1 && tObj->Target != GL_TEXTURE_3D)
 315       surf[0] |= GEN7_SURFACE_IS_ARRAY;
 316
 317    if (mt->array_spacing_lod0)
 318       surf[0] |= GEN7_SURFACE_ARYSPC_LOD0;
 319
 320    surf[1] = mt->region->bo->offset + mt->offset; /* reloc */
 321    surf[1] += intel_miptree_get_tile_offsets(intelObj->mt, firstImage->Level, 0,
 322                                              &tile_x, &tile_y);
 323
 324    surf[2] = SET_FIELD(mt->logical_width0 - 1, GEN7_SURFACE_WIDTH) |
 325              SET_FIELD(mt->logical_height0 - 1, GEN7_SURFACE_HEIGHT);
 326    surf[3] = SET_FIELD(mt->logical_depth0 - 1, BRW_SURFACE_DEPTH) |
 327              ((intelObj->mt->region->pitch) - 1);
 328
 329    surf[4] = gen7_surface_msaa_bits(mt->num_samples, mt->msaa_layout);
 330
 331    assert(brw->has_surface_tile_offset || (tile_x == 0 && tile_y == 0));
 332    /* Note that the low bits of these fields are missing, so
 333     * there's the possibility of getting in trouble.
 334     */
 335    surf[5] = ((tile_x / 4) << BRW_SURFACE_X_OFFSET_SHIFT |
 336               (tile_y / 2) << BRW_SURFACE_Y_OFFSET_SHIFT |
 337               SET_FIELD(GEN7_MOCS_L3, GEN7_SURFACE_MOCS) |
 338               /* mip count */
 339               (intelObj->_MaxLevel - tObj->BaseLevel));
 340
 341    if (brw->is_haswell) {
 342       /* Handling GL_ALPHA as a surface format override breaks 1.30+ style
 343        * texturing functions that return a float, as our code generation always
 344        * selects the .x channel (which would always be 0).
 345        */
 346       const bool alpha_depth = tObj->DepthMode == GL_ALPHA &&
 347          (firstImage->_BaseFormat == GL_DEPTH_COMPONENT ||
 348           firstImage->_BaseFormat == GL_DEPTH_STENCIL);
 349
 350       const int swizzle = unlikely(alpha_depth)
 351          ? SWIZZLE_XYZW : brw_get_texture_swizzle(ctx, tObj);
 352
 353       surf[7] =
 354          SET_FIELD(swizzle_to_scs(GET_SWZ(swizzle, 0)), GEN7_SURFACE_SCS_R) |
 355          SET_FIELD(swizzle_to_scs(GET_SWZ(swizzle, 1)), GEN7_SURFACE_SCS_G) |
 356          SET_FIELD(swizzle_to_scs(GET_SWZ(swizzle, 2)), GEN7_SURFACE_SCS_B) |
 357          SET_FIELD(swizzle_to_scs(GET_SWZ(swizzle, 3)), GEN7_SURFACE_SCS_A);
 358    }
 359
 360    /* Emit relocation to surface contents */
 361    drm_intel_bo_emit_reloc(brw->batch.bo,
 362                            binding_table[surf_index] + 4,
 363                            intelObj->mt->region->bo,
 364                            surf[1] - intelObj->mt->region->bo->offset,
 365                            I915_GEM_DOMAIN_SAMPLER, 0);
 366
 367    gen7_check_surface_setup(surf, false /* is_render_target */);
 368 }
 369
 370 /**
 371  * Create the constant buffer surface.  Vertex/fragment shader constants will
 372  * be read from this buffer with Data Port Read instructions/messages.
 373  */
 374 static void
 375 gen7_create_constant_surface(struct brw_context *brw,
 376                              drm_intel_bo *bo,
 377                              uint32_t offset,
 378                              uint32_t size,
 379                              uint32_t *out_offset,
 380                              bool dword_pitch)
 381 {
 382    uint32_t stride = dword_pitch ? 4 : 16;
 383    uint32_t elements = ALIGN(size, stride) / stride;
 384    const GLint w = elements - 1;
 385
 386    uint32_t *surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE,
 387                                     8 * 4, 32, out_offset);
 388    memset(surf, 0, 8 * 4);
 389
 390    surf[0] = BRW_SURFACE_BUFFER << BRW_SURFACE_TYPE_SHIFT |
 391              BRW_SURFACEFORMAT_R32G32B32A32_FLOAT << BRW_SURFACE_FORMAT_SHIFT |
 392              BRW_SURFACE_RC_READ_WRITE;
 393
 394    assert(bo);
 395    surf[1] = bo->offset + offset; /* reloc */
 396
 397    /* note that these differ from GEN6 */
 398    surf[2] = SET_FIELD(w & 0x7f, GEN7_SURFACE_WIDTH) |
 399              SET_FIELD((w >> 7) & 0x3fff, GEN7_SURFACE_HEIGHT);
 400    surf[3] = SET_FIELD((w >> 21) & 0x3f, BRW_SURFACE_DEPTH) |
 401              (stride - 1);
 402
 403    if (brw->is_haswell) {
 404       surf[7] = SET_FIELD(HSW_SCS_RED,   GEN7_SURFACE_SCS_R) |
 405                 SET_FIELD(HSW_SCS_GREEN, GEN7_SURFACE_SCS_G) |
 406                 SET_FIELD(HSW_SCS_BLUE,  GEN7_SURFACE_SCS_B) |
 407                 SET_FIELD(HSW_SCS_ALPHA, GEN7_SURFACE_SCS_A);
 408    }
 409
 410    drm_intel_bo_emit_reloc(brw->batch.bo,
 411                            *out_offset + 4,
 412                            bo, offset,
 413                            I915_GEM_DOMAIN_SAMPLER, 0);
 414
 415    gen7_check_surface_setup(surf, false /* is_render_target */);
 416 }
 417
 418 /**
 419  * Create a surface for shader time.
 420  */
 421 void
 422 gen7_create_shader_time_surface(struct brw_context *brw, uint32_t *out_offset)
 423 {
 424    const int w = brw->shader_time.bo->size - 1;
 425
 426    uint32_t *surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE,
 427                                     8 * 4, 32, out_offset);
 428    memset(surf, 0, 8 * 4);
 429
 430    surf[0] = BRW_SURFACE_BUFFER << BRW_SURFACE_TYPE_SHIFT |
 431              BRW_SURFACEFORMAT_RAW << BRW_SURFACE_FORMAT_SHIFT |
 432              BRW_SURFACE_RC_READ_WRITE;
 433
 434    surf[1] = brw->shader_time.bo->offset; /* reloc */
 435
 436    /* note that these differ from GEN6 */
 437    surf[2] = SET_FIELD(w & 0x7f, GEN7_SURFACE_WIDTH) |
 438              SET_FIELD((w >> 7) & 0x3fff, GEN7_SURFACE_HEIGHT);
 439    surf[3] = SET_FIELD((w >> 21) & 0x3f, BRW_SURFACE_DEPTH);
 440
 441    /* Unlike texture or renderbuffer surfaces, we only do untyped operations
 442     * on the shader_time surface, so there's no need to set HSW channel
 443     * overrides.
 444     */
 445
 446    drm_intel_bo_emit_reloc(brw->batch.bo,
 447                            *out_offset + 4,
 448                            brw->shader_time.bo, 0,
 449                            I915_GEM_DOMAIN_SAMPLER, 0);
 450
 451    gen7_check_surface_setup(surf, false /* is_render_target */);
 452 }
 453
 454 static void
 455 gen7_update_null_renderbuffer_surface(struct brw_context *brw, unsigned unit)
 456 {
 457    /* From the Ivy bridge PRM, Vol4 Part1 p62 (Surface Type: Programming
 458     * Notes):
 459     *
 460     *     A null surface is used in instances where an actual surface is not
 461     *     bound. When a write message is generated to a null surface, no
 462     *     actual surface is written to. When a read message (including any
 463     *     sampling engine message) is generated to a null surface, the result
 464     *     is all zeros. Note that a null surface type is allowed to be used
 465     *     with all messages, even if it is not specificially indicated as
 466     *     supported. All of the remaining fields in surface state are ignored
 467     *     for null surfaces, with the following exceptions: Width, Height,
 468     *     Depth, LOD, and Render Target View Extent fields must match the
 469     *     depth buffer’s corresponding state for all render target surfaces,
 470     *     including null.
 471     */
 472    struct gl_context *ctx = &brw->ctx;
 473
 474    /* _NEW_BUFFERS */
 475    const struct gl_framebuffer *fb = ctx->DrawBuffer;
 476
 477    uint32_t *surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE, 8 * 4, 32,
 478                                     &brw->wm.surf_offset[SURF_INDEX_DRAW(unit)]);
 479    memset(surf, 0, 8 * 4);
 480
 481    /* From the Ivybridge PRM, Volume 4, Part 1, page 65,
 482     * Tiled Surface: Programming Notes:
 483     * "If Surface Type is SURFTYPE_NULL, this field must be TRUE."
 484     */
 485    surf[0] = BRW_SURFACE_NULL << BRW_SURFACE_TYPE_SHIFT |
 486              BRW_SURFACEFORMAT_B8G8R8A8_UNORM << BRW_SURFACE_FORMAT_SHIFT |
 487              GEN7_SURFACE_TILING_Y;
 488
 489    surf[2] = SET_FIELD(fb->Width - 1, GEN7_SURFACE_WIDTH) |
 490              SET_FIELD(fb->Height - 1, GEN7_SURFACE_HEIGHT);
 491
 492    gen7_check_surface_setup(surf, true /* is_render_target */);
 493 }
 494
 495 /**
 496  * Sets up a surface state structure to point at the given region.
 497  * While it is only used for the front/back buffer currently, it should be
 498  * usable for further buffers when doing ARB_draw_buffer support.
 499  */
 500 static void
 501 gen7_update_renderbuffer_surface(struct brw_context *brw,
 502                                  struct gl_renderbuffer *rb,
 503                                  bool layered,
 504                                  unsigned int unit)
 505 {
 506    struct gl_context *ctx = &brw->ctx;
 507    struct intel_renderbuffer *irb = intel_renderbuffer(rb);
 508    struct intel_region *region = irb->mt->region;
 509    uint32_t format;
 510    /* _NEW_BUFFERS */
 511    gl_format rb_format = _mesa_get_render_format(ctx, intel_rb_format(irb));
 512    uint32_t surftype;
 513    bool is_array = false;
 514    int depth = MAX2(rb->Depth, 1);
 515    int min_array_element;
 516    const uint8_t mocs = GEN7_MOCS_L3;
 517    GLenum gl_target = rb->TexImage ?
 518                          rb->TexImage->TexObject->Target : GL_TEXTURE_2D;
 519
 520    uint32_t surf_index = SURF_INDEX_DRAW(unit);
 521
 522    uint32_t *surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE, 8 * 4, 32,
 523                                     &brw->wm.surf_offset[surf_index]);
 524    memset(surf, 0, 8 * 4);
 525
 526    intel_miptree_used_for_rendering(irb->mt);
 527
 528    /* Render targets can't use IMS layout */
 529    assert(irb->mt->msaa_layout != INTEL_MSAA_LAYOUT_IMS);
 530
 531    assert(brw_render_target_supported(brw, rb));
 532    format = brw->render_target_format[rb_format];
 533    if (unlikely(!brw->format_supported_as_render_target[rb_format])) {
 534       _mesa_problem(ctx, "%s: renderbuffer format %s unsupported\n",
 535                     __FUNCTION__, _mesa_get_format_name(rb_format));
 536    }
 537
 538    switch (gl_target) {
 539    case GL_TEXTURE_CUBE_MAP_ARRAY:
 540    case GL_TEXTURE_CUBE_MAP:
 541       surftype = BRW_SURFACE_2D;
 542       is_array = true;
 543       depth *= 6;
 544       break;
 545    default:
 546       surftype = translate_tex_target(gl_target);
 547       is_array = _mesa_tex_target_is_array(gl_target);
 548       break;
 549    }
 550
 551    if (layered) {
 552       min_array_element = 0;
 553    } else if (irb->mt->num_samples > 1) {
 554       min_array_element = irb->mt_layer / irb->mt->num_samples;
 555    } else {
 556       min_array_element = irb->mt_layer;
 557    }
 558
 559    surf[0] = surftype << BRW_SURFACE_TYPE_SHIFT |
 560              format << BRW_SURFACE_FORMAT_SHIFT |
 561              (irb->mt->array_spacing_lod0 ? GEN7_SURFACE_ARYSPC_LOD0
 562                                           : GEN7_SURFACE_ARYSPC_FULL) |
 563              gen7_surface_tiling_mode(region->tiling);
 564
 565    if (irb->mt->align_h == 4)
 566       surf[0] |= GEN7_SURFACE_VALIGN_4;
 567    if (irb->mt->align_w == 8)
 568       surf[0] |= GEN7_SURFACE_HALIGN_8;
 569
 570    if (is_array) {
 571       surf[0] |= GEN7_SURFACE_IS_ARRAY;
 572    }
 573
 574    surf[1] = region->bo->offset;
 575
 576    assert(brw->has_surface_tile_offset);
 577
 578    surf[5] = SET_FIELD(mocs, GEN7_SURFACE_MOCS) |
 579              (irb->mt_level - irb->mt->first_level);
 580
 581    surf[2] = SET_FIELD(irb->mt->logical_width0 - 1, GEN7_SURFACE_WIDTH) |
 582              SET_FIELD(irb->mt->logical_height0 - 1, GEN7_SURFACE_HEIGHT);
 583
 584    surf[3] = ((depth - 1) << BRW_SURFACE_DEPTH_SHIFT) |
 585              (region->pitch - 1);
 586
 587    surf[4] = gen7_surface_msaa_bits(irb->mt->num_samples, irb->mt->msaa_layout) |
 588              min_array_element << GEN7_SURFACE_MIN_ARRAY_ELEMENT_SHIFT |
 589              (depth - 1) << GEN7_SURFACE_RENDER_TARGET_VIEW_EXTENT_SHIFT;
 590
 591    if (irb->mt->mcs_mt) {
 592       gen7_set_surface_mcs_info(brw, surf, brw->wm.surf_offset[surf_index],
 593                                 irb->mt->mcs_mt, true /* is RT */);
 594    }
 595
 596    surf[7] = irb->mt->fast_clear_color_value;
 597
 598    if (brw->is_haswell) {
 599       surf[7] |= (SET_FIELD(HSW_SCS_RED,   GEN7_SURFACE_SCS_R) |
 600                   SET_FIELD(HSW_SCS_GREEN, GEN7_SURFACE_SCS_G) |
 601                   SET_FIELD(HSW_SCS_BLUE,  GEN7_SURFACE_SCS_B) |
 602                   SET_FIELD(HSW_SCS_ALPHA, GEN7_SURFACE_SCS_A));
 603    }
 604
 605    drm_intel_bo_emit_reloc(brw->batch.bo,
 606                            brw->wm.surf_offset[surf_index] + 4,
 607                            region->bo,
 608                            surf[1] - region->bo->offset,
 609                            I915_GEM_DOMAIN_RENDER,
 610                            I915_GEM_DOMAIN_RENDER);
 611
 612    gen7_check_surface_setup(surf, true /* is_render_target */);
 613 }
 614
 615 void
 616 gen7_init_vtable_surface_functions(struct brw_context *brw)
 617 {
 618    brw->vtbl.update_texture_surface = gen7_update_texture_surface;
 619    brw->vtbl.update_renderbuffer_surface = gen7_update_renderbuffer_surface;
 620    brw->vtbl.update_null_renderbuffer_surface =
 621       gen7_update_null_renderbuffer_surface;
 622    brw->vtbl.create_constant_surface = gen7_create_constant_surface;
 623 }