src/mesa/drivers/dri/i965/gen7_wm_surface_state.c

   1 /*
   2  * Copyright © 2011 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23 #include "main/mtypes.h"
  24 #include "main/blend.h"
  25 #include "main/samplerobj.h"
  26 #include "main/texformat.h"
  27 #include "program/prog_parameter.h"
  28
  29 #include "intel_mipmap_tree.h"
  30 #include "intel_batchbuffer.h"
  31 #include "intel_tex.h"
  32 #include "intel_fbo.h"
  33 #include "intel_buffer_objects.h"
  34
  35 #include "brw_context.h"
  36 #include "brw_state.h"
  37 #include "brw_defines.h"
  38 #include "brw_wm.h"
  39
  40 /**
  41  * Convert an swizzle enumeration (i.e. SWIZZLE_X) to one of the Gen7.5+
  42  * "Shader Channel Select" enumerations (i.e. HSW_SCS_RED)
  43  */
  44 static unsigned
  45 swizzle_to_scs(GLenum swizzle)
  46 {
  47    switch (swizzle) {
  48    case SWIZZLE_X:
  49       return HSW_SCS_RED;
  50    case SWIZZLE_Y:
  51       return HSW_SCS_GREEN;
  52    case SWIZZLE_Z:
  53       return HSW_SCS_BLUE;
  54    case SWIZZLE_W:
  55       return HSW_SCS_ALPHA;
  56    case SWIZZLE_ZERO:
  57       return HSW_SCS_ZERO;
  58    case SWIZZLE_ONE:
  59       return HSW_SCS_ONE;
  60    }
  61
  62    assert(!"Should not get here: invalid swizzle mode");
  63    return HSW_SCS_ZERO;
  64 }
  65
  66 uint32_t
  67 gen7_surface_tiling_mode(uint32_t tiling)
  68 {
  69    switch (tiling) {
  70    case I915_TILING_X:
  71       return GEN7_SURFACE_TILING_X;
  72    case I915_TILING_Y:
  73       return GEN7_SURFACE_TILING_Y;
  74    default:
  75       return GEN7_SURFACE_TILING_NONE;
  76    }
  77 }
  78
  79
  80 uint32_t
  81 gen7_surface_msaa_bits(unsigned num_samples, enum intel_msaa_layout layout)
  82 {
  83    uint32_t ss4 = 0;
  84
  85    if (num_samples > 4)
  86       ss4 |= GEN7_SURFACE_MULTISAMPLECOUNT_8;
  87    else if (num_samples > 1)
  88       ss4 |= GEN7_SURFACE_MULTISAMPLECOUNT_4;
  89    else
  90       ss4 |= GEN7_SURFACE_MULTISAMPLECOUNT_1;
  91
  92    if (layout == INTEL_MSAA_LAYOUT_IMS)
  93       ss4 |= GEN7_SURFACE_MSFMT_DEPTH_STENCIL;
  94    else
  95       ss4 |= GEN7_SURFACE_MSFMT_MSS;
  96
  97    return ss4;
  98 }
  99
 100
 101 void
 102 gen7_set_surface_mcs_info(struct brw_context *brw,
 103                           uint32_t *surf,
 104                           uint32_t surf_offset,
 105                           const struct intel_mipmap_tree *mcs_mt,
 106                           bool is_render_target)
 107 {
 108    /* From the Ivy Bridge PRM, Vol4 Part1 p76, "MCS Base Address":
 109     *
 110     *     "The MCS surface must be stored as Tile Y."
 111     */
 112    assert(mcs_mt->region->tiling == I915_TILING_Y);
 113
 114    /* Compute the pitch in units of tiles.  To do this we need to divide the
 115     * pitch in bytes by 128, since a single Y-tile is 128 bytes wide.
 116     */
 117    unsigned pitch_tiles = mcs_mt->region->pitch / 128;
 118
 119    /* The upper 20 bits of surface state DWORD 6 are the upper 20 bits of the
 120     * GPU address of the MCS buffer; the lower 12 bits contain other control
 121     * information.  Since buffer addresses are always on 4k boundaries (and
 122     * thus have their lower 12 bits zero), we can use an ordinary reloc to do
 123     * the necessary address translation.
 124     */
 125    assert ((mcs_mt->region->bo->offset & 0xfff) == 0);
 126
 127    surf[6] = GEN7_SURFACE_MCS_ENABLE |
 128              SET_FIELD(pitch_tiles - 1, GEN7_SURFACE_MCS_PITCH) |
 129              mcs_mt->region->bo->offset;
 130
 131    drm_intel_bo_emit_reloc(brw->intel.batch.bo,
 132                            surf_offset + 6 * 4,
 133                            mcs_mt->region->bo,
 134                            surf[6] & 0xfff,
 135                            is_render_target ? I915_GEM_DOMAIN_RENDER
 136                            : I915_GEM_DOMAIN_SAMPLER,
 137                            is_render_target ? I915_GEM_DOMAIN_RENDER : 0);
 138 }
 139
 140
 141 void
 142 gen7_check_surface_setup(uint32_t *surf, bool is_render_target)
 143 {
 144    unsigned num_multisamples = surf[4] & INTEL_MASK(5, 3);
 145    unsigned multisampled_surface_storage_format = surf[4] & (1 << 6);
 146    unsigned surface_array_spacing = surf[0] & (1 << 10);
 147    bool is_multisampled = num_multisamples != GEN7_SURFACE_MULTISAMPLECOUNT_1;
 148
 149    (void) surface_array_spacing;
 150
 151    /* From the Graphics BSpec: vol5c Shared Functions [SNB+] > State >
 152     * SURFACE_STATE > SURFACE_STATE for most messages [DevIVB]: Surface Array
 153     * Spacing:
 154     *
 155     *   If Multisampled Surface Storage Format is MSFMT_MSS and Number of
 156     *   Multisamples is not MULTISAMPLECOUNT_1, this field must be set to
 157     *   ARYSPC_LOD0.
 158     */
 159    if (multisampled_surface_storage_format == GEN7_SURFACE_MSFMT_MSS
 160        && is_multisampled)
 161       assert(surface_array_spacing == GEN7_SURFACE_ARYSPC_LOD0);
 162
 163    /* From the Graphics BSpec: vol5c Shared Functions [SNB+] > State >
 164     * SURFACE_STATE > SURFACE_STATE for most messages [DevIVB]: Multisampled
 165     * Surface Storage Format:
 166     *
 167     *   All multisampled render target surfaces must have this field set to
 168     *   MSFMT_MSS.
 169     *
 170     * But also:
 171     *
 172     *   This field is ignored if Number of Multisamples is MULTISAMPLECOUNT_1.
 173     */
 174    if (is_render_target && is_multisampled) {
 175       assert(multisampled_surface_storage_format == GEN7_SURFACE_MSFMT_MSS);
 176    }
 177
 178    /* From the Graphics BSpec: vol5c Shared Functions [SNB+] > State >
 179     * SURFACE_STATE > SURFACE_STATE for most messages [DevIVB]: Multisampled
 180     * Surface Storage Format:
 181     *
 182     *   If the surface’s Number of Multisamples is MULTISAMPLECOUNT_8, Width
 183     *   is >= 8192 (meaning the actual surface width is >= 8193 pixels), this
 184     *   field must be set to MSFMT_MSS.
 185     */
 186    uint32_t width = GET_FIELD(surf[2], GEN7_SURFACE_WIDTH) + 1;
 187    if (num_multisamples == GEN7_SURFACE_MULTISAMPLECOUNT_8 && width >= 8193) {
 188       assert(multisampled_surface_storage_format == GEN7_SURFACE_MSFMT_MSS);
 189    }
 190
 191    /* From the Graphics BSpec: vol5c Shared Functions [SNB+] > State >
 192     * SURFACE_STATE > SURFACE_STATE for most messages [DevIVB]: Multisampled
 193     * Surface Storage Format:
 194     *
 195     *   If the surface’s Number of Multisamples is MULTISAMPLECOUNT_8,
 196     *   ((Depth+1) * (Height+1)) is > 4,194,304, OR if the surface’s Number of
 197     *   Multisamples is MULTISAMPLECOUNT_4, ((Depth+1) * (Height+1)) is >
 198     *   8,388,608, this field must be set to MSFMT_DEPTH_STENCIL.This field
 199     *   must be set to MSFMT_DEPTH_STENCIL if Surface Format is one of the
 200     *   following: I24X8_UNORM, L24X8_UNORM, A24X8_UNORM, or
 201     *   R24_UNORM_X8_TYPELESS.
 202     *
 203     * But also:
 204     *
 205     *   This field is ignored if Number of Multisamples is MULTISAMPLECOUNT_1.
 206     */
 207    uint32_t depth = GET_FIELD(surf[3], BRW_SURFACE_DEPTH) + 1;
 208    uint32_t height = GET_FIELD(surf[2], GEN7_SURFACE_HEIGHT) + 1;
 209    if (num_multisamples == GEN7_SURFACE_MULTISAMPLECOUNT_8 &&
 210        depth * height > 4194304) {
 211       assert(multisampled_surface_storage_format ==
 212              GEN7_SURFACE_MSFMT_DEPTH_STENCIL);
 213    }
 214    if (num_multisamples == GEN7_SURFACE_MULTISAMPLECOUNT_4 &&
 215        depth * height > 8388608) {
 216       assert(multisampled_surface_storage_format ==
 217              GEN7_SURFACE_MSFMT_DEPTH_STENCIL);
 218    }
 219    if (is_multisampled) {
 220       switch (GET_FIELD(surf[0], BRW_SURFACE_FORMAT)) {
 221       case BRW_SURFACEFORMAT_I24X8_UNORM:
 222       case BRW_SURFACEFORMAT_L24X8_UNORM:
 223       case BRW_SURFACEFORMAT_A24X8_UNORM:
 224       case BRW_SURFACEFORMAT_R24_UNORM_X8_TYPELESS:
 225          assert(multisampled_surface_storage_format ==
 226                 GEN7_SURFACE_MSFMT_DEPTH_STENCIL);
 227       }
 228    }
 229 }
 230
 231
 232 static void
 233 gen7_update_buffer_texture_surface(struct gl_context *ctx,
 234                                    unsigned unit,
 235                                    uint32_t *binding_table,
 236                                    unsigned surf_index)
 237 {
 238    struct brw_context *brw = brw_context(ctx);
 239    struct intel_context *intel = &brw->intel;
 240    struct gl_texture_object *tObj = ctx->Texture.Unit[unit]._Current;
 241    struct intel_buffer_object *intel_obj =
 242       intel_buffer_object(tObj->BufferObject);
 243    drm_intel_bo *bo = intel_obj ? intel_obj->buffer : NULL;
 244    gl_format format = tObj->_BufferObjectFormat;
 245
 246    uint32_t *surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE,
 247                                     8 * 4, 32, &binding_table[surf_index]);
 248    memset(surf, 0, 8 * 4);
 249
 250    uint32_t surface_format = brw_format_for_mesa_format(format);
 251    if (surface_format == 0 && format != MESA_FORMAT_RGBA_FLOAT32) {
 252       _mesa_problem(NULL, "bad format %s for texture buffer\n",
 253                     _mesa_get_format_name(format));
 254    }
 255
 256    surf[0] = BRW_SURFACE_BUFFER << BRW_SURFACE_TYPE_SHIFT |
 257              surface_format << BRW_SURFACE_FORMAT_SHIFT |
 258              BRW_SURFACE_RC_READ_WRITE;
 259
 260    if (bo) {
 261       surf[1] = bo->offset; /* reloc */
 262
 263       /* Emit relocation to surface contents.  Section 5.1.1 of the gen4
 264        * bspec ("Data Cache") says that the data cache does not exist as
 265        * a separate cache and is just the sampler cache.
 266        */
 267       drm_intel_bo_emit_reloc(intel->batch.bo,
 268                               binding_table[surf_index] + 4,
 269                               bo, 0,
 270                               I915_GEM_DOMAIN_SAMPLER, 0);
 271
 272       int texel_size = _mesa_get_format_bytes(format);
 273       int w = intel_obj->Base.Size / texel_size;
 274
 275       /* note that these differ from GEN6 */
 276       surf[2] = SET_FIELD(w & 0x7f, GEN7_SURFACE_WIDTH) | /* bits 6:0 of size */
 277                 SET_FIELD((w >> 7) & 0x3fff, GEN7_SURFACE_HEIGHT); /* 20:7 */
 278       surf[3] = SET_FIELD((w >> 21) & 0x3f, BRW_SURFACE_DEPTH) | /* bits 26:21 */
 279                 (texel_size - 1);
 280    }
 281
 282    gen7_check_surface_setup(surf, false /* is_render_target */);
 283 }
 284
 285 static void
 286 gen7_update_texture_surface(struct gl_context *ctx,
 287                             unsigned unit,
 288                             uint32_t *binding_table,
 289                             unsigned surf_index)
 290 {
 291    struct brw_context *brw = brw_context(ctx);
 292    struct intel_context *intel = &brw->intel;
 293    struct gl_texture_object *tObj = ctx->Texture.Unit[unit]._Current;
 294    struct intel_texture_object *intelObj = intel_texture_object(tObj);
 295    struct intel_mipmap_tree *mt = intelObj->mt;
 296    struct gl_texture_image *firstImage = tObj->Image[0][tObj->BaseLevel];
 297    struct gl_sampler_object *sampler = _mesa_get_samplerobj(ctx, unit);
 298    uint32_t tile_x, tile_y;
 299
 300    if (tObj->Target == GL_TEXTURE_BUFFER) {
 301       gen7_update_buffer_texture_surface(ctx, unit, binding_table, surf_index);
 302       return;
 303    }
 304
 305    uint32_t *surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE,
 306                                     8 * 4, 32, &binding_table[surf_index]);
 307    memset(surf, 0, 8 * 4);
 308
 309    uint32_t tex_format = translate_tex_format(intel,
 310                                               mt->format,
 311                                               tObj->DepthMode,
 312                                               sampler->sRGBDecode);
 313
 314    surf[0] = translate_tex_target(tObj->Target) << BRW_SURFACE_TYPE_SHIFT |
 315              tex_format << BRW_SURFACE_FORMAT_SHIFT |
 316              gen7_surface_tiling_mode(mt->region->tiling) |
 317              BRW_SURFACE_CUBEFACE_ENABLES;
 318
 319    if (mt->align_h == 4)
 320       surf[0] |= GEN7_SURFACE_VALIGN_4;
 321    if (mt->align_w == 8)
 322       surf[0] |= GEN7_SURFACE_HALIGN_8;
 323
 324    if (mt->logical_depth0 > 1 && tObj->Target != GL_TEXTURE_3D)
 325       surf[0] |= GEN7_SURFACE_IS_ARRAY;
 326
 327    if (mt->array_spacing_lod0)
 328       surf[0] |= GEN7_SURFACE_ARYSPC_LOD0;
 329
 330    surf[1] = mt->region->bo->offset + mt->offset; /* reloc */
 331    surf[1] += intel_miptree_get_tile_offsets(intelObj->mt, firstImage->Level, 0,
 332                                              &tile_x, &tile_y);
 333
 334    surf[2] = SET_FIELD(mt->logical_width0 - 1, GEN7_SURFACE_WIDTH) |
 335              SET_FIELD(mt->logical_height0 - 1, GEN7_SURFACE_HEIGHT);
 336    surf[3] = SET_FIELD(mt->logical_depth0 - 1, BRW_SURFACE_DEPTH) |
 337              ((intelObj->mt->region->pitch) - 1);
 338
 339    surf[4] = gen7_surface_msaa_bits(mt->num_samples, mt->msaa_layout);
 340
 341    assert(brw->has_surface_tile_offset || (tile_x == 0 && tile_y == 0));
 342    /* Note that the low bits of these fields are missing, so
 343     * there's the possibility of getting in trouble.
 344     */
 345    surf[5] = ((tile_x / 4) << BRW_SURFACE_X_OFFSET_SHIFT |
 346               (tile_y / 2) << BRW_SURFACE_Y_OFFSET_SHIFT |
 347               /* mip count */
 348               (intelObj->_MaxLevel - tObj->BaseLevel));
 349
 350    if (intel->is_haswell) {
 351       /* Handling GL_ALPHA as a surface format override breaks 1.30+ style
 352        * texturing functions that return a float, as our code generation always
 353        * selects the .x channel (which would always be 0).
 354        */
 355       const bool alpha_depth = tObj->DepthMode == GL_ALPHA &&
 356          (firstImage->_BaseFormat == GL_DEPTH_COMPONENT ||
 357           firstImage->_BaseFormat == GL_DEPTH_STENCIL);
 358
 359       const int swizzle = unlikely(alpha_depth)
 360          ? SWIZZLE_XYZW : brw_get_texture_swizzle(ctx, tObj);
 361
 362       surf[7] =
 363          SET_FIELD(swizzle_to_scs(GET_SWZ(swizzle, 0)), GEN7_SURFACE_SCS_R) |
 364          SET_FIELD(swizzle_to_scs(GET_SWZ(swizzle, 1)), GEN7_SURFACE_SCS_G) |
 365          SET_FIELD(swizzle_to_scs(GET_SWZ(swizzle, 2)), GEN7_SURFACE_SCS_B) |
 366          SET_FIELD(swizzle_to_scs(GET_SWZ(swizzle, 3)), GEN7_SURFACE_SCS_A);
 367    }
 368
 369    /* Emit relocation to surface contents */
 370    drm_intel_bo_emit_reloc(brw->intel.batch.bo,
 371                            binding_table[surf_index] + 4,
 372                            intelObj->mt->region->bo,
 373                            surf[1] - intelObj->mt->region->bo->offset,
 374                            I915_GEM_DOMAIN_SAMPLER, 0);
 375
 376    gen7_check_surface_setup(surf, false /* is_render_target */);
 377 }
 378
 379 /**
 380  * Create the constant buffer surface.  Vertex/fragment shader constants will
 381  * be read from this buffer with Data Port Read instructions/messages.
 382  */
 383 static void
 384 gen7_create_constant_surface(struct brw_context *brw,
 385                              drm_intel_bo *bo,
 386                              uint32_t offset,
 387                              uint32_t size,
 388                              uint32_t *out_offset,
 389                              bool dword_pitch)
 390 {
 391    struct intel_context *intel = &brw->intel;
 392    uint32_t stride = dword_pitch ? 4 : 16;
 393    uint32_t elements = ALIGN(size, stride) / stride;
 394    const GLint w = elements - 1;
 395
 396    uint32_t *surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE,
 397                                     8 * 4, 32, out_offset);
 398    memset(surf, 0, 8 * 4);
 399
 400    surf[0] = BRW_SURFACE_BUFFER << BRW_SURFACE_TYPE_SHIFT |
 401              BRW_SURFACEFORMAT_R32G32B32A32_FLOAT << BRW_SURFACE_FORMAT_SHIFT |
 402              BRW_SURFACE_RC_READ_WRITE;
 403
 404    assert(bo);
 405    surf[1] = bo->offset + offset; /* reloc */
 406
 407    /* note that these differ from GEN6 */
 408    surf[2] = SET_FIELD(w & 0x7f, GEN7_SURFACE_WIDTH) |
 409              SET_FIELD((w >> 7) & 0x3fff, GEN7_SURFACE_HEIGHT);
 410    surf[3] = SET_FIELD((w >> 21) & 0x3f, BRW_SURFACE_DEPTH) |
 411              (stride - 1);
 412
 413    if (intel->is_haswell) {
 414       surf[7] = SET_FIELD(HSW_SCS_RED,   GEN7_SURFACE_SCS_R) |
 415                 SET_FIELD(HSW_SCS_GREEN, GEN7_SURFACE_SCS_G) |
 416                 SET_FIELD(HSW_SCS_BLUE,  GEN7_SURFACE_SCS_B) |
 417                 SET_FIELD(HSW_SCS_ALPHA, GEN7_SURFACE_SCS_A);
 418    }
 419
 420    /* Emit relocation to surface contents.  Section 5.1.1 of the gen4
 421     * bspec ("Data Cache") says that the data cache does not exist as
 422     * a separate cache and is just the sampler cache.
 423     */
 424    drm_intel_bo_emit_reloc(intel->batch.bo,
 425                            *out_offset + 4,
 426                            bo, offset,
 427                            I915_GEM_DOMAIN_SAMPLER, 0);
 428
 429    gen7_check_surface_setup(surf, false /* is_render_target */);
 430 }
 431
 432 /**
 433  * Create a surface for shader time.
 434  */
 435 void
 436 gen7_create_shader_time_surface(struct brw_context *brw, uint32_t *out_offset)
 437 {
 438    struct intel_context *intel = &brw->intel;
 439    const int w = brw->shader_time.bo->size - 1;
 440
 441    uint32_t *surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE,
 442                                     8 * 4, 32, out_offset);
 443    memset(surf, 0, 8 * 4);
 444
 445    surf[0] = BRW_SURFACE_BUFFER << BRW_SURFACE_TYPE_SHIFT |
 446              BRW_SURFACEFORMAT_RAW << BRW_SURFACE_FORMAT_SHIFT |
 447              BRW_SURFACE_RC_READ_WRITE;
 448
 449    surf[1] = brw->shader_time.bo->offset; /* reloc */
 450
 451    /* note that these differ from GEN6 */
 452    surf[2] = SET_FIELD(w & 0x7f, GEN7_SURFACE_WIDTH) |
 453              SET_FIELD((w >> 7) & 0x3fff, GEN7_SURFACE_HEIGHT);
 454    surf[3] = SET_FIELD((w >> 21) & 0x3f, BRW_SURFACE_DEPTH);
 455
 456    /* Unlike texture or renderbuffer surfaces, we only do untyped operations
 457     * on the shader_time surface, so there's no need to set HSW channel
 458     * overrides.
 459     */
 460
 461    /* Emit relocation to surface contents.  Section 5.1.1 of the gen4
 462     * bspec ("Data Cache") says that the data cache does not exist as
 463     * a separate cache and is just the sampler cache.
 464     */
 465    drm_intel_bo_emit_reloc(intel->batch.bo,
 466                            *out_offset + 4,
 467                            brw->shader_time.bo, 0,
 468                            I915_GEM_DOMAIN_SAMPLER, 0);
 469
 470    gen7_check_surface_setup(surf, false /* is_render_target */);
 471 }
 472
 473 static void
 474 gen7_update_null_renderbuffer_surface(struct brw_context *brw, unsigned unit)
 475 {
 476    /* From the Ivy bridge PRM, Vol4 Part1 p62 (Surface Type: Programming
 477     * Notes):
 478     *
 479     *     A null surface is used in instances where an actual surface is not
 480     *     bound. When a write message is generated to a null surface, no
 481     *     actual surface is written to. When a read message (including any
 482     *     sampling engine message) is generated to a null surface, the result
 483     *     is all zeros. Note that a null surface type is allowed to be used
 484     *     with all messages, even if it is not specificially indicated as
 485     *     supported. All of the remaining fields in surface state are ignored
 486     *     for null surfaces, with the following exceptions: Width, Height,
 487     *     Depth, LOD, and Render Target View Extent fields must match the
 488     *     depth buffer’s corresponding state for all render target surfaces,
 489     *     including null.
 490     */
 491    struct intel_context *intel = &brw->intel;
 492    struct gl_context *ctx = &intel->ctx;
 493
 494    /* _NEW_BUFFERS */
 495    const struct gl_framebuffer *fb = ctx->DrawBuffer;
 496
 497    uint32_t *surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE,
 498                                     8 * 4, 32, &brw->wm.surf_offset[unit]);
 499    memset(surf, 0, 8 * 4);
 500
 501    /* From the Ivybridge PRM, Volume 4, Part 1, page 65,
 502     * Tiled Surface: Programming Notes:
 503     * "If Surface Type is SURFTYPE_NULL, this field must be TRUE."
 504     */
 505    surf[0] = BRW_SURFACE_NULL << BRW_SURFACE_TYPE_SHIFT |
 506              BRW_SURFACEFORMAT_B8G8R8A8_UNORM << BRW_SURFACE_FORMAT_SHIFT |
 507              GEN7_SURFACE_TILING_Y;
 508
 509    surf[2] = SET_FIELD(fb->Width - 1, GEN7_SURFACE_WIDTH) |
 510              SET_FIELD(fb->Height - 1, GEN7_SURFACE_HEIGHT);
 511
 512    gen7_check_surface_setup(surf, true /* is_render_target */);
 513 }
 514
 515 /**
 516  * Sets up a surface state structure to point at the given region.
 517  * While it is only used for the front/back buffer currently, it should be
 518  * usable for further buffers when doing ARB_draw_buffer support.
 519  */
 520 static void
 521 gen7_update_renderbuffer_surface(struct brw_context *brw,
 522                                  struct gl_renderbuffer *rb,
 523                                  bool layered,
 524                                  unsigned int unit)
 525 {
 526    struct intel_context *intel = &brw->intel;
 527    struct gl_context *ctx = &intel->ctx;
 528    struct intel_renderbuffer *irb = intel_renderbuffer(rb);
 529    struct intel_region *region = irb->mt->region;
 530    uint32_t format;
 531    /* _NEW_BUFFERS */
 532    gl_format rb_format = _mesa_get_render_format(ctx, intel_rb_format(irb));
 533    uint32_t surftype;
 534    bool is_array = false;
 535    int depth = MAX2(rb->Depth, 1);
 536    int min_array_element;
 537    GLenum gl_target = rb->TexImage ?
 538                          rb->TexImage->TexObject->Target : GL_TEXTURE_2D;
 539
 540    uint32_t *surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE,
 541                                     8 * 4, 32, &brw->wm.surf_offset[unit]);
 542    memset(surf, 0, 8 * 4);
 543
 544    intel_miptree_used_for_rendering(irb->mt);
 545
 546    /* Render targets can't use IMS layout */
 547    assert(irb->mt->msaa_layout != INTEL_MSAA_LAYOUT_IMS);
 548
 549    assert(brw_render_target_supported(intel, rb));
 550    format = brw->render_target_format[rb_format];
 551    if (unlikely(!brw->format_supported_as_render_target[rb_format])) {
 552       _mesa_problem(ctx, "%s: renderbuffer format %s unsupported\n",
 553                     __FUNCTION__, _mesa_get_format_name(rb_format));
 554    }
 555
 556    switch (gl_target) {
 557    case GL_TEXTURE_CUBE_MAP_ARRAY:
 558    case GL_TEXTURE_CUBE_MAP:
 559       surftype = BRW_SURFACE_2D;
 560       is_array = true;
 561       depth *= 6;
 562       break;
 563    default:
 564       surftype = translate_tex_target(gl_target);
 565       is_array = _mesa_tex_target_is_array(gl_target);
 566       break;
 567    }
 568
 569    if (layered) {
 570       min_array_element = 0;
 571    } else if (irb->mt->num_samples > 1) {
 572       min_array_element = irb->mt_layer / irb->mt->num_samples;
 573    } else {
 574       min_array_element = irb->mt_layer;
 575    }
 576
 577    surf[0] = surftype << BRW_SURFACE_TYPE_SHIFT |
 578              format << BRW_SURFACE_FORMAT_SHIFT |
 579              (irb->mt->array_spacing_lod0 ? GEN7_SURFACE_ARYSPC_LOD0
 580                                           : GEN7_SURFACE_ARYSPC_FULL) |
 581              gen7_surface_tiling_mode(region->tiling);
 582
 583    if (irb->mt->align_h == 4)
 584       surf[0] |= GEN7_SURFACE_VALIGN_4;
 585    if (irb->mt->align_w == 8)
 586       surf[0] |= GEN7_SURFACE_HALIGN_8;
 587
 588    if (is_array) {
 589       surf[0] |= GEN7_SURFACE_IS_ARRAY;
 590    }
 591
 592    surf[1] = region->bo->offset;
 593
 594    assert(brw->has_surface_tile_offset);
 595
 596    surf[5] = irb->mt_level - irb->mt->first_level;
 597
 598    surf[2] = SET_FIELD(irb->mt->logical_width0 - 1, GEN7_SURFACE_WIDTH) |
 599              SET_FIELD(irb->mt->logical_height0 - 1, GEN7_SURFACE_HEIGHT);
 600
 601    surf[3] = ((depth - 1) << BRW_SURFACE_DEPTH_SHIFT) |
 602              (region->pitch - 1);
 603
 604    surf[4] = gen7_surface_msaa_bits(irb->mt->num_samples, irb->mt->msaa_layout) |
 605              min_array_element << GEN7_SURFACE_MIN_ARRAY_ELEMENT_SHIFT |
 606              (depth - 1) << GEN7_SURFACE_RENDER_TARGET_VIEW_EXTENT_SHIFT;
 607
 608    if (irb->mt->mcs_mt) {
 609       gen7_set_surface_mcs_info(brw, surf, brw->wm.surf_offset[unit],
 610                                 irb->mt->mcs_mt, true /* is RT */);
 611    }
 612
 613    surf[7] = irb->mt->fast_clear_color_value;
 614
 615    if (intel->is_haswell) {
 616       surf[7] |= (SET_FIELD(HSW_SCS_RED,   GEN7_SURFACE_SCS_R) |
 617                   SET_FIELD(HSW_SCS_GREEN, GEN7_SURFACE_SCS_G) |
 618                   SET_FIELD(HSW_SCS_BLUE,  GEN7_SURFACE_SCS_B) |
 619                   SET_FIELD(HSW_SCS_ALPHA, GEN7_SURFACE_SCS_A));
 620    }
 621
 622    drm_intel_bo_emit_reloc(brw->intel.batch.bo,
 623                            brw->wm.surf_offset[unit] + 4,
 624                            region->bo,
 625                            surf[1] - region->bo->offset,
 626                            I915_GEM_DOMAIN_RENDER,
 627                            I915_GEM_DOMAIN_RENDER);
 628
 629    gen7_check_surface_setup(surf, true /* is_render_target */);
 630 }
 631
 632 void
 633 gen7_init_vtable_surface_functions(struct brw_context *brw)
 634 {
 635    struct intel_context *intel = &brw->intel;
 636
 637    intel->vtbl.update_texture_surface = gen7_update_texture_surface;
 638    intel->vtbl.update_renderbuffer_surface = gen7_update_renderbuffer_surface;
 639    intel->vtbl.update_null_renderbuffer_surface =
 640       gen7_update_null_renderbuffer_surface;
 641    intel->vtbl.create_constant_surface = gen7_create_constant_surface;
 642 }