src/mesa/drivers/dri/i965/gen7_wm_surface_state.c

   1 /*
   2  * Copyright © 2011 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23 #include "main/mtypes.h"
  24 #include "main/samplerobj.h"
  25 #include "program/prog_parameter.h"
  26
  27 #include "intel_mipmap_tree.h"
  28 #include "intel_batchbuffer.h"
  29 #include "intel_tex.h"
  30 #include "intel_fbo.h"
  31
  32 #include "brw_context.h"
  33 #include "brw_state.h"
  34 #include "brw_defines.h"
  35 #include "brw_wm.h"
  36
  37 static void
  38 gen7_set_surface_tiling(struct gen7_surface_state *surf, uint32_t tiling)
  39 {
  40    switch (tiling) {
  41    case I915_TILING_NONE:
  42       surf->ss0.tiled_surface = 0;
  43       surf->ss0.tile_walk = 0;
  44       break;
  45    case I915_TILING_X:
  46       surf->ss0.tiled_surface = 1;
  47       surf->ss0.tile_walk = BRW_TILEWALK_XMAJOR;
  48       break;
  49    case I915_TILING_Y:
  50       surf->ss0.tiled_surface = 1;
  51       surf->ss0.tile_walk = BRW_TILEWALK_YMAJOR;
  52       break;
  53    }
  54 }
  55
  56 static void
  57 gen7_update_texture_surface(struct gl_context *ctx, GLuint unit)
  58 {
  59    struct brw_context *brw = brw_context(ctx);
  60    struct gl_texture_object *tObj = ctx->Texture.Unit[unit]._Current;
  61    struct intel_texture_object *intelObj = intel_texture_object(tObj);
  62    struct gl_texture_image *firstImage = tObj->Image[0][tObj->BaseLevel];
  63    struct gl_sampler_object *sampler = _mesa_get_samplerobj(ctx, unit);
  64    const GLuint surf_index = SURF_INDEX_TEXTURE(unit);
  65    struct gen7_surface_state *surf;
  66    int width, height, depth;
  67
  68    intel_miptree_get_dimensions_for_image(firstImage, &width, &height, &depth);
  69
  70    surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE,
  71                           sizeof(*surf), 32, &brw->wm.surf_offset[surf_index]);
  72    memset(surf, 0, sizeof(*surf));
  73
  74    surf->ss0.surface_type = translate_tex_target(tObj->Target);
  75    surf->ss0.surface_format = translate_tex_format(firstImage->TexFormat,
  76                                                    firstImage->InternalFormat,
  77                                                    sampler->DepthMode,
  78                                                    sampler->sRGBDecode);
  79    if (tObj->Target == GL_TEXTURE_CUBE_MAP) {
  80       surf->ss0.cube_pos_x = 1;
  81       surf->ss0.cube_pos_y = 1;
  82       surf->ss0.cube_pos_z = 1;
  83       surf->ss0.cube_neg_x = 1;
  84       surf->ss0.cube_neg_y = 1;
  85       surf->ss0.cube_neg_z = 1;
  86    }
  87
  88    gen7_set_surface_tiling(surf, intelObj->mt->region->tiling);
  89
  90    /* ss0 remaining fields:
  91     * - is_array
  92     * - vertical_alignment
  93     * - horizontal_alignment
  94     * - vert_line_stride (exists on gen6 but we ignore it)
  95     * - vert_line_stride_ofs (exists on gen6 but we ignore it)
  96     * - surface_array_spacing
  97     * - render_cache_read_write (exists on gen6 but ignored here)
  98     */
  99
 100    surf->ss1.base_addr = intelObj->mt->region->bo->offset; /* reloc */
 101
 102    surf->ss2.width = width - 1;
 103    surf->ss2.height = height - 1;
 104
 105    surf->ss3.pitch = (intelObj->mt->region->pitch * intelObj->mt->cpp) - 1;
 106    surf->ss3.depth = depth - 1;
 107
 108    /* ss4: ignored? */
 109
 110    surf->ss5.mip_count = intelObj->_MaxLevel - tObj->BaseLevel;
 111    surf->ss5.min_lod = 0;
 112
 113    /* ss5 remaining fields:
 114     * - x_offset (N/A for textures?)
 115     * - y_offset (ditto)
 116     * - cache_control
 117     */
 118
 119    /* Emit relocation to surface contents */
 120    drm_intel_bo_emit_reloc(brw->intel.batch.bo,
 121                            brw->wm.surf_offset[surf_index] +
 122                            offsetof(struct gen7_surface_state, ss1),
 123                            intelObj->mt->region->bo, 0,
 124                            I915_GEM_DOMAIN_SAMPLER, 0);
 125 }
 126
 127 /**
 128  * Create the constant buffer surface.  Vertex/fragment shader constants will
 129  * be read from this buffer with Data Port Read instructions/messages.
 130  */
 131 void
 132 gen7_create_constant_surface(struct brw_context *brw,
 133                              drm_intel_bo *bo,
 134                              int width,
 135                              uint32_t *out_offset)
 136 {
 137    const GLint w = width - 1;
 138    struct gen7_surface_state *surf;
 139
 140    surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE,
 141                           sizeof(*surf), 32, out_offset);
 142    memset(surf, 0, sizeof(*surf));
 143
 144    surf->ss0.surface_type = BRW_SURFACE_BUFFER;
 145    surf->ss0.surface_format = BRW_SURFACEFORMAT_R32G32B32A32_FLOAT;
 146
 147    surf->ss0.render_cache_read_write = 1;
 148
 149    assert(bo);
 150    surf->ss1.base_addr = bo->offset; /* reloc */
 151
 152    surf->ss2.width = w & 0x7f;            /* bits 6:0 of size or width */
 153    surf->ss2.height = (w >> 7) & 0x1fff;  /* bits 19:7 of size or width */
 154    surf->ss3.depth = (w >> 20) & 0x7f;    /* bits 26:20 of size or width */
 155    surf->ss3.pitch = (width * 16) - 1; /* ignored?? */
 156    gen7_set_surface_tiling(surf, I915_TILING_NONE); /* tiling now allowed */
 157
 158    /* Emit relocation to surface contents.  Section 5.1.1 of the gen4
 159     * bspec ("Data Cache") says that the data cache does not exist as
 160     * a separate cache and is just the sampler cache.
 161     */
 162    drm_intel_bo_emit_reloc(brw->intel.batch.bo,
 163                            (*out_offset +
 164                             offsetof(struct gen7_surface_state, ss1)),
 165                            bo, 0,
 166                            I915_GEM_DOMAIN_SAMPLER, 0);
 167 }
 168
 169 /**
 170  * Updates surface / buffer for fragment shader constant buffer, if
 171  * one is required.
 172  *
 173  * This consumes the state updates for the constant buffer, and produces
 174  * BRW_NEW_WM_SURFACES to get picked up by brw_prepare_wm_surfaces for
 175  * inclusion in the binding table.
 176  */
 177 static void upload_wm_constant_surface(struct brw_context *brw)
 178 {
 179    GLuint surf = SURF_INDEX_FRAG_CONST_BUFFER;
 180    struct brw_fragment_program *fp =
 181       (struct brw_fragment_program *) brw->fragment_program;
 182    const struct gl_program_parameter_list *params =
 183       fp->program.Base.Parameters;
 184
 185    /* If there's no constant buffer, then no surface BO is needed to point at
 186     * it.
 187     */
 188    if (brw->wm.const_bo == 0) {
 189       if (brw->wm.surf_offset[surf]) {
 190          brw->state.dirty.brw |= BRW_NEW_WM_SURFACES;
 191          brw->wm.surf_offset[surf] = 0;
 192       }
 193       return;
 194    }
 195
 196    gen7_create_constant_surface(brw, brw->wm.const_bo, params->NumParameters,
 197                                 &brw->wm.surf_offset[surf]);
 198    brw->state.dirty.brw |= BRW_NEW_WM_SURFACES;
 199 }
 200
 201 const struct brw_tracked_state gen7_wm_constant_surface = {
 202    .dirty = {
 203       .mesa = 0,
 204       .brw = (BRW_NEW_WM_CONSTBUF |
 205               BRW_NEW_BATCH),
 206       .cache = 0
 207    },
 208    .emit = upload_wm_constant_surface,
 209 };
 210
 211 static void
 212 gen7_update_null_renderbuffer_surface(struct brw_context *brw, unsigned unit)
 213 {
 214    struct gen7_surface_state *surf;
 215
 216    surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE,
 217                           sizeof(*surf), 32, &brw->wm.surf_offset[unit]);
 218    memset(surf, 0, sizeof(*surf));
 219
 220    surf->ss0.surface_type = BRW_SURFACE_NULL;
 221    surf->ss0.surface_format = BRW_SURFACEFORMAT_B8G8R8A8_UNORM;
 222 }
 223
 224 /**
 225  * Sets up a surface state structure to point at the given region.
 226  * While it is only used for the front/back buffer currently, it should be
 227  * usable for further buffers when doing ARB_draw_buffer support.
 228  */
 229 static void
 230 gen7_update_renderbuffer_surface(struct brw_context *brw,
 231                                  struct gl_renderbuffer *rb,
 232                                  unsigned int unit)
 233 {
 234    struct intel_context *intel = &brw->intel;
 235    struct gl_context *ctx = &intel->ctx;
 236    struct intel_renderbuffer *irb = intel_renderbuffer(rb);
 237    struct intel_region *region = irb->region;
 238    struct gen7_surface_state *surf;
 239    uint32_t tile_x, tile_y;
 240
 241    surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE,
 242                           sizeof(*surf), 32, &brw->wm.surf_offset[unit]);
 243    memset(surf, 0, sizeof(*surf));
 244
 245    switch (irb->Base.Format) {
 246    case MESA_FORMAT_XRGB8888:
 247       /* XRGB is handled as ARGB because the chips in this family
 248        * cannot render to XRGB targets.  This means that we have to
 249        * mask writes to alpha (ala glColorMask) and reconfigure the
 250        * alpha blending hardware to use GL_ONE (or GL_ZERO) for
 251        * cases where GL_DST_ALPHA (or GL_ONE_MINUS_DST_ALPHA) is
 252        * used.
 253        */
 254       surf->ss0.surface_format = BRW_SURFACEFORMAT_B8G8R8A8_UNORM;
 255       break;
 256    case MESA_FORMAT_INTENSITY_FLOAT32:
 257    case MESA_FORMAT_LUMINANCE_FLOAT32:
 258       /* For these formats, we just need to read/write the first
 259        * channel into R, which is to say that we just treat them as
 260        * GL_RED.
 261        */
 262       surf->ss0.surface_format = BRW_SURFACEFORMAT_R32_FLOAT;
 263       break;
 264    case MESA_FORMAT_SARGB8:
 265       /* without GL_EXT_framebuffer_sRGB we shouldn't bind sRGB
 266          surfaces to the blend/update as sRGB */
 267       if (ctx->Color.sRGBEnabled)
 268          surf->ss0.surface_format = brw_format_for_mesa_format(irb->Base.Format);
 269       else
 270          surf->ss0.surface_format = BRW_SURFACEFORMAT_B8G8R8A8_UNORM;
 271       break;
 272    default:
 273       assert(brw_render_target_supported(irb->Base.Format));
 274       surf->ss0.surface_format = brw_format_for_mesa_format(irb->Base.Format);
 275    }
 276
 277    surf->ss0.surface_type = BRW_SURFACE_2D;
 278    /* reloc */
 279    surf->ss1.base_addr = intel_renderbuffer_tile_offsets(irb, &tile_x, &tile_y);
 280    surf->ss1.base_addr += region->bo->offset; /* reloc */
 281
 282    assert(brw->has_surface_tile_offset);
 283    /* Note that the low bits of these fields are missing, so
 284     * there's the possibility of getting in trouble.
 285     */
 286    assert(tile_x % 4 == 0);
 287    assert(tile_y % 2 == 0);
 288    surf->ss5.x_offset = tile_x / 4;
 289    surf->ss5.y_offset = tile_y / 2;
 290
 291    surf->ss2.width = rb->Width - 1;
 292    surf->ss2.height = rb->Height - 1;
 293    gen7_set_surface_tiling(surf, region->tiling);
 294    surf->ss3.pitch = (region->pitch * region->cpp) - 1;
 295
 296    drm_intel_bo_emit_reloc(brw->intel.batch.bo,
 297                            brw->wm.surf_offset[unit] +
 298                            offsetof(struct gen7_surface_state, ss1),
 299                            region->bo,
 300                            surf->ss1.base_addr - region->bo->offset,
 301                            I915_GEM_DOMAIN_RENDER,
 302                            I915_GEM_DOMAIN_RENDER);
 303 }
 304
 305 static void
 306 prepare_wm_surfaces(struct brw_context *brw)
 307 {
 308    struct gl_context *ctx = &brw->intel.ctx;
 309    int i;
 310    int nr_surfaces = 0;
 311
 312    if (ctx->DrawBuffer->_NumColorDrawBuffers >= 1) {
 313       for (i = 0; i < ctx->DrawBuffer->_NumColorDrawBuffers; i++) {
 314          struct gl_renderbuffer *rb = ctx->DrawBuffer->_ColorDrawBuffers[i];
 315          struct intel_renderbuffer *irb = intel_renderbuffer(rb);
 316          struct intel_region *region = irb ? irb->region : NULL;
 317
 318          if (region)
 319             brw_add_validated_bo(brw, region->bo);
 320          nr_surfaces = SURF_INDEX_DRAW(i) + 1;
 321       }
 322    }
 323
 324    if (brw->wm.const_bo) {
 325       brw_add_validated_bo(brw, brw->wm.const_bo);
 326       nr_surfaces = SURF_INDEX_FRAG_CONST_BUFFER + 1;
 327    }
 328
 329    for (i = 0; i < BRW_MAX_TEX_UNIT; i++) {
 330       const struct gl_texture_unit *texUnit = &ctx->Texture.Unit[i];
 331       struct gl_texture_object *tObj = texUnit->_Current;
 332       struct intel_texture_object *intelObj = intel_texture_object(tObj);
 333
 334       if (texUnit->_ReallyEnabled) {
 335          brw_add_validated_bo(brw, intelObj->mt->region->bo);
 336          nr_surfaces = SURF_INDEX_TEXTURE(i) + 1;
 337       }
 338    }
 339
 340    /* Have to update this in our prepare, since the unit's prepare
 341     * relies on it.
 342     */
 343    if (brw->wm.nr_surfaces != nr_surfaces) {
 344       brw->wm.nr_surfaces = nr_surfaces;
 345       brw->state.dirty.brw |= BRW_NEW_NR_WM_SURFACES;
 346    }
 347 }
 348
 349 /**
 350  * Constructs the set of surface state objects pointed to by the
 351  * binding table.
 352  */
 353 static void
 354 upload_wm_surfaces(struct brw_context *brw)
 355 {
 356    struct gl_context *ctx = &brw->intel.ctx;
 357    GLuint i;
 358
 359    /* _NEW_BUFFERS | _NEW_COLOR */
 360    /* Update surfaces for drawing buffers */
 361    if (ctx->DrawBuffer->_NumColorDrawBuffers >= 1) {
 362       for (i = 0; i < ctx->DrawBuffer->_NumColorDrawBuffers; i++) {
 363          if (intel_renderbuffer(ctx->DrawBuffer->_ColorDrawBuffers[i])) {
 364             gen7_update_renderbuffer_surface(brw,
 365                ctx->DrawBuffer->_ColorDrawBuffers[i], i);
 366          } else {
 367             gen7_update_null_renderbuffer_surface(brw, i);
 368          }
 369       }
 370    } else {
 371       gen7_update_null_renderbuffer_surface(brw, 0);
 372    }
 373
 374    /* Update surfaces for textures */
 375    for (i = 0; i < BRW_MAX_TEX_UNIT; i++) {
 376       const struct gl_texture_unit *texUnit = &ctx->Texture.Unit[i];
 377       const GLuint surf = SURF_INDEX_TEXTURE(i);
 378
 379       /* _NEW_TEXTURE */
 380       if (texUnit->_ReallyEnabled) {
 381          gen7_update_texture_surface(ctx, i);
 382       } else {
 383          brw->wm.surf_offset[surf] = 0;
 384       }
 385    }
 386
 387    brw->state.dirty.brw |= BRW_NEW_WM_SURFACES;
 388 }
 389
 390 const struct brw_tracked_state gen7_wm_surfaces = {
 391    .dirty = {
 392       .mesa = (_NEW_COLOR |
 393                _NEW_TEXTURE |
 394                _NEW_BUFFERS),
 395       .brw = BRW_NEW_BATCH,
 396       .cache = 0
 397    },
 398    .prepare = prepare_wm_surfaces,
 399    .emit = upload_wm_surfaces,
 400 };