src/mesa/drivers/dri/i965/gen7_wm_surface_state.c

   1 /*
   2  * Copyright © 2011 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23 #include "main/mtypes.h"
  24 #include "main/samplerobj.h"
  25 #include "program/prog_parameter.h"
  26
  27 #include "intel_mipmap_tree.h"
  28 #include "intel_batchbuffer.h"
  29 #include "intel_tex.h"
  30 #include "intel_fbo.h"
  31 #include "intel_buffer_objects.h"
  32
  33 #include "brw_context.h"
  34 #include "brw_state.h"
  35 #include "brw_defines.h"
  36 #include "brw_wm.h"
  37
  38 void
  39 gen7_set_surface_tiling(struct gen7_surface_state *surf, uint32_t tiling)
  40 {
  41    switch (tiling) {
  42    case I915_TILING_NONE:
  43       surf->ss0.tiled_surface = 0;
  44       surf->ss0.tile_walk = 0;
  45       break;
  46    case I915_TILING_X:
  47       surf->ss0.tiled_surface = 1;
  48       surf->ss0.tile_walk = BRW_TILEWALK_XMAJOR;
  49       break;
  50    case I915_TILING_Y:
  51       surf->ss0.tiled_surface = 1;
  52       surf->ss0.tile_walk = BRW_TILEWALK_YMAJOR;
  53       break;
  54    }
  55 }
  56
  57 static void
  58 gen7_update_buffer_texture_surface(struct gl_context *ctx, GLuint unit)
  59 {
  60    struct brw_context *brw = brw_context(ctx);
  61    struct gl_texture_object *tObj = ctx->Texture.Unit[unit]._Current;
  62    const GLuint surf_index = SURF_INDEX_TEXTURE(unit);
  63    struct gen7_surface_state *surf;
  64    struct intel_buffer_object *intel_obj =
  65       intel_buffer_object(tObj->BufferObject);
  66    drm_intel_bo *bo = intel_obj ? intel_obj->buffer : NULL;
  67    gl_format format = tObj->_BufferObjectFormat;
  68    int texel_size = _mesa_get_format_bytes(format);
  69
  70    surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE,
  71                           sizeof(*surf), 32, &brw->wm.surf_offset[surf_index]);
  72    memset(surf, 0, sizeof(*surf));
  73
  74    surf->ss0.surface_type = BRW_SURFACE_BUFFER;
  75    surf->ss0.surface_format = brw_format_for_mesa_format(format);
  76
  77    surf->ss0.render_cache_read_write = 1;
  78
  79    if (surf->ss0.surface_format == 0 && format != MESA_FORMAT_RGBA_FLOAT32) {
  80       _mesa_problem(NULL, "bad format %s for texture buffer\n",
  81                     _mesa_get_format_name(format));
  82    }
  83
  84    if (bo) {
  85       surf->ss1.base_addr = bo->offset; /* reloc */
  86
  87       /* Emit relocation to surface contents.  Section 5.1.1 of the gen4
  88        * bspec ("Data Cache") says that the data cache does not exist as
  89        * a separate cache and is just the sampler cache.
  90        */
  91       drm_intel_bo_emit_reloc(brw->intel.batch.bo,
  92                               (brw->wm.surf_offset[surf_index] +
  93                                offsetof(struct gen7_surface_state, ss1)),
  94                               bo, 0,
  95                               I915_GEM_DOMAIN_SAMPLER, 0);
  96
  97       int w = intel_obj->Base.Size / texel_size;
  98       surf->ss2.width = w & 0x7f;            /* bits 6:0 of size or width */
  99       surf->ss2.height = (w >> 7) & 0x1fff;  /* bits 19:7 of size or width */
 100       surf->ss3.depth = (w >> 20) & 0x7f;    /* bits 26:20 of size or width */
 101       surf->ss3.pitch = texel_size - 1;
 102 } else {
 103       surf->ss1.base_addr = 0;
 104       surf->ss2.width = 0;
 105       surf->ss2.height = 0;
 106       surf->ss3.depth = 0;
 107       surf->ss3.pitch = 0;
 108    }
 109
 110    gen7_set_surface_tiling(surf, I915_TILING_NONE);
 111 }
 112
 113 static void
 114 gen7_update_texture_surface(struct gl_context *ctx, GLuint unit)
 115 {
 116    struct brw_context *brw = brw_context(ctx);
 117    struct gl_texture_object *tObj = ctx->Texture.Unit[unit]._Current;
 118    struct intel_texture_object *intelObj = intel_texture_object(tObj);
 119    struct intel_mipmap_tree *mt = intelObj->mt;
 120    struct gl_texture_image *firstImage = tObj->Image[0][tObj->BaseLevel];
 121    struct gl_sampler_object *sampler = _mesa_get_samplerobj(ctx, unit);
 122    const GLuint surf_index = SURF_INDEX_TEXTURE(unit);
 123    struct gen7_surface_state *surf;
 124    int width, height, depth;
 125
 126    if (tObj->Target == GL_TEXTURE_BUFFER) {
 127       gen7_update_buffer_texture_surface(ctx, unit);
 128       return;
 129    }
 130
 131    intel_miptree_get_dimensions_for_image(firstImage, &width, &height, &depth);
 132
 133    surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE,
 134                           sizeof(*surf), 32, &brw->wm.surf_offset[surf_index]);
 135    memset(surf, 0, sizeof(*surf));
 136
 137    if (mt->align_h == 4)
 138       surf->ss0.vertical_alignment = 1;
 139    if (mt->align_w == 8)
 140       surf->ss0.horizontal_alignment = 1;
 141
 142    surf->ss0.surface_type = translate_tex_target(tObj->Target);
 143    surf->ss0.surface_format = translate_tex_format(mt->format,
 144                                                    firstImage->InternalFormat,
 145                                                    sampler->DepthMode,
 146                                                    sampler->sRGBDecode);
 147    if (tObj->Target == GL_TEXTURE_CUBE_MAP) {
 148       surf->ss0.cube_pos_x = 1;
 149       surf->ss0.cube_pos_y = 1;
 150       surf->ss0.cube_pos_z = 1;
 151       surf->ss0.cube_neg_x = 1;
 152       surf->ss0.cube_neg_y = 1;
 153       surf->ss0.cube_neg_z = 1;
 154    }
 155
 156    surf->ss0.is_array = depth > 1 && tObj->Target != GL_TEXTURE_3D;
 157
 158    gen7_set_surface_tiling(surf, intelObj->mt->region->tiling);
 159
 160    /* ss0 remaining fields:
 161     * - vert_line_stride (exists on gen6 but we ignore it)
 162     * - vert_line_stride_ofs (exists on gen6 but we ignore it)
 163     * - surface_array_spacing
 164     * - render_cache_read_write (exists on gen6 but ignored here)
 165     */
 166
 167    surf->ss1.base_addr = intelObj->mt->region->bo->offset; /* reloc */
 168
 169    surf->ss2.width = width - 1;
 170    surf->ss2.height = height - 1;
 171
 172    surf->ss3.pitch = (intelObj->mt->region->pitch * intelObj->mt->cpp) - 1;
 173    surf->ss3.depth = depth - 1;
 174
 175    /* ss4: ignored? */
 176
 177    surf->ss5.mip_count = intelObj->_MaxLevel - tObj->BaseLevel;
 178    surf->ss5.min_lod = 0;
 179
 180    /* ss5 remaining fields:
 181     * - x_offset (N/A for textures?)
 182     * - y_offset (ditto)
 183     * - cache_control
 184     */
 185
 186    if (brw->intel.is_haswell) {
 187       surf->ss7.shader_chanel_select_r = HSW_SCS_RED;
 188       surf->ss7.shader_chanel_select_g = HSW_SCS_GREEN;
 189       surf->ss7.shader_chanel_select_b = HSW_SCS_BLUE;
 190       surf->ss7.shader_chanel_select_a = HSW_SCS_ALPHA;
 191    }
 192
 193    /* Emit relocation to surface contents */
 194    drm_intel_bo_emit_reloc(brw->intel.batch.bo,
 195                            brw->wm.surf_offset[surf_index] +
 196                            offsetof(struct gen7_surface_state, ss1),
 197                            intelObj->mt->region->bo, 0,
 198                            I915_GEM_DOMAIN_SAMPLER, 0);
 199 }
 200
 201 /**
 202  * Create the constant buffer surface.  Vertex/fragment shader constants will
 203  * be read from this buffer with Data Port Read instructions/messages.
 204  */
 205 void
 206 gen7_create_constant_surface(struct brw_context *brw,
 207                              drm_intel_bo *bo,
 208                              int width,
 209                              uint32_t *out_offset)
 210 {
 211    const GLint w = width - 1;
 212    struct gen7_surface_state *surf;
 213
 214    surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE,
 215                           sizeof(*surf), 32, out_offset);
 216    memset(surf, 0, sizeof(*surf));
 217
 218    surf->ss0.surface_type = BRW_SURFACE_BUFFER;
 219    surf->ss0.surface_format = BRW_SURFACEFORMAT_R32G32B32A32_FLOAT;
 220
 221    surf->ss0.render_cache_read_write = 1;
 222
 223    assert(bo);
 224    surf->ss1.base_addr = bo->offset; /* reloc */
 225
 226    surf->ss2.width = w & 0x7f;            /* bits 6:0 of size or width */
 227    surf->ss2.height = (w >> 7) & 0x1fff;  /* bits 19:7 of size or width */
 228    surf->ss3.depth = (w >> 20) & 0x7f;    /* bits 26:20 of size or width */
 229    surf->ss3.pitch = (16 - 1); /* stride between samples */
 230    gen7_set_surface_tiling(surf, I915_TILING_NONE); /* tiling now allowed */
 231
 232    if (brw->intel.is_haswell) {
 233       surf->ss7.shader_chanel_select_r = HSW_SCS_RED;
 234       surf->ss7.shader_chanel_select_g = HSW_SCS_GREEN;
 235       surf->ss7.shader_chanel_select_b = HSW_SCS_BLUE;
 236       surf->ss7.shader_chanel_select_a = HSW_SCS_ALPHA;
 237    }
 238
 239    /* Emit relocation to surface contents.  Section 5.1.1 of the gen4
 240     * bspec ("Data Cache") says that the data cache does not exist as
 241     * a separate cache and is just the sampler cache.
 242     */
 243    drm_intel_bo_emit_reloc(brw->intel.batch.bo,
 244                            (*out_offset +
 245                             offsetof(struct gen7_surface_state, ss1)),
 246                            bo, 0,
 247                            I915_GEM_DOMAIN_SAMPLER, 0);
 248 }
 249
 250 static void
 251 gen7_update_null_renderbuffer_surface(struct brw_context *brw, unsigned unit)
 252 {
 253    struct gen7_surface_state *surf;
 254
 255    surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE,
 256                           sizeof(*surf), 32, &brw->wm.surf_offset[unit]);
 257    memset(surf, 0, sizeof(*surf));
 258
 259    surf->ss0.surface_type = BRW_SURFACE_NULL;
 260    surf->ss0.surface_format = BRW_SURFACEFORMAT_B8G8R8A8_UNORM;
 261 }
 262
 263 /**
 264  * Sets up a surface state structure to point at the given region.
 265  * While it is only used for the front/back buffer currently, it should be
 266  * usable for further buffers when doing ARB_draw_buffer support.
 267  */
 268 static void
 269 gen7_update_renderbuffer_surface(struct brw_context *brw,
 270                                  struct gl_renderbuffer *rb,
 271                                  unsigned int unit)
 272 {
 273    struct intel_context *intel = &brw->intel;
 274    struct gl_context *ctx = &intel->ctx;
 275    struct intel_renderbuffer *irb = intel_renderbuffer(rb);
 276    struct intel_region *region = irb->mt->region;
 277    struct gen7_surface_state *surf;
 278    uint32_t tile_x, tile_y;
 279    gl_format rb_format = intel_rb_format(irb);
 280
 281    surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE,
 282                           sizeof(*surf), 32, &brw->wm.surf_offset[unit]);
 283    memset(surf, 0, sizeof(*surf));
 284
 285    if (irb->mt->align_h == 4)
 286       surf->ss0.vertical_alignment = 1;
 287    if (irb->mt->align_w == 8)
 288       surf->ss0.horizontal_alignment = 1;
 289
 290    switch (rb_format) {
 291    case MESA_FORMAT_SARGB8:
 292       /* _NEW_BUFFERS
 293        *
 294        * Without GL_EXT_framebuffer_sRGB we shouldn't bind sRGB surfaces to the
 295        * blend/update as sRGB.
 296        */
 297       if (ctx->Color.sRGBEnabled)
 298          surf->ss0.surface_format = brw_format_for_mesa_format(rb_format);
 299       else
 300          surf->ss0.surface_format = BRW_SURFACEFORMAT_B8G8R8A8_UNORM;
 301       break;
 302    default:
 303       assert(brw_render_target_supported(intel, rb));
 304       surf->ss0.surface_format = brw->render_target_format[rb_format];
 305       if (unlikely(!brw->format_supported_as_render_target[rb_format])) {
 306          _mesa_problem(ctx, "%s: renderbuffer format %s unsupported\n",
 307                        __FUNCTION__, _mesa_get_format_name(rb_format));
 308       }
 309        break;
 310    }
 311
 312    surf->ss0.surface_type = BRW_SURFACE_2D;
 313    /* reloc */
 314    surf->ss1.base_addr = intel_renderbuffer_tile_offsets(irb, &tile_x, &tile_y);
 315    surf->ss1.base_addr += region->bo->offset; /* reloc */
 316
 317    assert(brw->has_surface_tile_offset);
 318    /* Note that the low bits of these fields are missing, so
 319     * there's the possibility of getting in trouble.
 320     */
 321    assert(tile_x % 4 == 0);
 322    assert(tile_y % 2 == 0);
 323    surf->ss5.x_offset = tile_x / 4;
 324    surf->ss5.y_offset = tile_y / 2;
 325
 326    surf->ss2.width = rb->Width - 1;
 327    surf->ss2.height = rb->Height - 1;
 328    gen7_set_surface_tiling(surf, region->tiling);
 329    surf->ss3.pitch = (region->pitch * region->cpp) - 1;
 330
 331    if (intel->is_haswell) {
 332       surf->ss7.shader_chanel_select_r = HSW_SCS_RED;
 333       surf->ss7.shader_chanel_select_g = HSW_SCS_GREEN;
 334       surf->ss7.shader_chanel_select_b = HSW_SCS_BLUE;
 335       surf->ss7.shader_chanel_select_a = HSW_SCS_ALPHA;
 336    }
 337
 338    drm_intel_bo_emit_reloc(brw->intel.batch.bo,
 339                            brw->wm.surf_offset[unit] +
 340                            offsetof(struct gen7_surface_state, ss1),
 341                            region->bo,
 342                            surf->ss1.base_addr - region->bo->offset,
 343                            I915_GEM_DOMAIN_RENDER,
 344                            I915_GEM_DOMAIN_RENDER);
 345 }
 346
 347 void
 348 gen7_init_vtable_surface_functions(struct brw_context *brw)
 349 {
 350    struct intel_context *intel = &brw->intel;
 351
 352    intel->vtbl.update_texture_surface = gen7_update_texture_surface;
 353    intel->vtbl.update_renderbuffer_surface = gen7_update_renderbuffer_surface;
 354    intel->vtbl.update_null_renderbuffer_surface =
 355       gen7_update_null_renderbuffer_surface;
 356    intel->vtbl.create_constant_surface = gen7_create_constant_surface;
 357 }