src/mesa/drivers/dri/i965/gen7_wm_surface_state.c

   1 /*
   2  * Copyright © 2011 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23 #include "main/mtypes.h"
  24 #include "main/samplerobj.h"
  25 #include "program/prog_parameter.h"
  26
  27 #include "intel_mipmap_tree.h"
  28 #include "intel_batchbuffer.h"
  29 #include "intel_tex.h"
  30 #include "intel_fbo.h"
  31 #include "intel_buffer_objects.h"
  32
  33 #include "brw_context.h"
  34 #include "brw_state.h"
  35 #include "brw_defines.h"
  36 #include "brw_wm.h"
  37
  38 /**
  39  * Convert an swizzle enumeration (i.e. SWIZZLE_X) to one of the Gen7.5+
  40  * "Shader Channel Select" enumerations (i.e. HSW_SCS_RED)
  41  */
  42 static unsigned
  43 swizzle_to_scs(GLenum swizzle)
  44 {
  45    switch (swizzle) {
  46    case SWIZZLE_X:
  47       return HSW_SCS_RED;
  48    case SWIZZLE_Y:
  49       return HSW_SCS_GREEN;
  50    case SWIZZLE_Z:
  51       return HSW_SCS_BLUE;
  52    case SWIZZLE_W:
  53       return HSW_SCS_ALPHA;
  54    case SWIZZLE_ZERO:
  55       return HSW_SCS_ZERO;
  56    case SWIZZLE_ONE:
  57       return HSW_SCS_ONE;
  58    }
  59
  60    assert(!"Should not get here: invalid swizzle mode");
  61    return HSW_SCS_ZERO;
  62 }
  63
  64 uint32_t
  65 gen7_surface_tiling_mode(uint32_t tiling)
  66 {
  67    switch (tiling) {
  68    case I915_TILING_X:
  69       return GEN7_SURFACE_TILING_X;
  70    case I915_TILING_Y:
  71       return GEN7_SURFACE_TILING_Y;
  72    default:
  73       return GEN7_SURFACE_TILING_NONE;
  74    }
  75 }
  76
  77
  78 uint32_t
  79 gen7_surface_msaa_bits(unsigned num_samples, enum intel_msaa_layout layout)
  80 {
  81    uint32_t ss4 = 0;
  82
  83    if (num_samples > 4)
  84       ss4 |= GEN7_SURFACE_MULTISAMPLECOUNT_8;
  85    else if (num_samples > 1)
  86       ss4 |= GEN7_SURFACE_MULTISAMPLECOUNT_4;
  87    else
  88       ss4 |= GEN7_SURFACE_MULTISAMPLECOUNT_1;
  89
  90    if (layout == INTEL_MSAA_LAYOUT_IMS)
  91       ss4 |= GEN7_SURFACE_MSFMT_DEPTH_STENCIL;
  92    else
  93       ss4 |= GEN7_SURFACE_MSFMT_MSS;
  94
  95    return ss4;
  96 }
  97
  98
  99 void
 100 gen7_set_surface_mcs_info(struct brw_context *brw,
 101                           uint32_t *surf,
 102                           uint32_t surf_offset,
 103                           const struct intel_mipmap_tree *mcs_mt,
 104                           bool is_render_target)
 105 {
 106    /* From the Ivy Bridge PRM, Vol4 Part1 p76, "MCS Base Address":
 107     *
 108     *     "The MCS surface must be stored as Tile Y."
 109     */
 110    assert(mcs_mt->region->tiling == I915_TILING_Y);
 111
 112    /* Compute the pitch in units of tiles.  To do this we need to divide the
 113     * pitch in bytes by 128, since a single Y-tile is 128 bytes wide.
 114     */
 115    unsigned pitch_tiles = mcs_mt->region->pitch / 128;
 116
 117    /* The upper 20 bits of surface state DWORD 6 are the upper 20 bits of the
 118     * GPU address of the MCS buffer; the lower 12 bits contain other control
 119     * information.  Since buffer addresses are always on 4k boundaries (and
 120     * thus have their lower 12 bits zero), we can use an ordinary reloc to do
 121     * the necessary address translation.
 122     */
 123    assert ((mcs_mt->region->bo->offset & 0xfff) == 0);
 124
 125    surf[6] = GEN7_SURFACE_MCS_ENABLE |
 126              SET_FIELD(pitch_tiles - 1, GEN7_SURFACE_MCS_PITCH) |
 127              mcs_mt->region->bo->offset;
 128
 129    drm_intel_bo_emit_reloc(brw->intel.batch.bo,
 130                            surf_offset + 6 * 4,
 131                            mcs_mt->region->bo,
 132                            surf[6] & 0xfff,
 133                            is_render_target ? I915_GEM_DOMAIN_RENDER
 134                            : I915_GEM_DOMAIN_SAMPLER,
 135                            is_render_target ? I915_GEM_DOMAIN_RENDER : 0);
 136 }
 137
 138
 139 void
 140 gen7_check_surface_setup(uint32_t *surf, bool is_render_target)
 141 {
 142    unsigned num_multisamples = surf[4] & INTEL_MASK(5, 3);
 143    unsigned multisampled_surface_storage_format = surf[4] & (1 << 6);
 144    unsigned surface_array_spacing = surf[0] & (1 << 10);
 145    bool is_multisampled = num_multisamples != GEN7_SURFACE_MULTISAMPLECOUNT_1;
 146
 147    (void) surface_array_spacing;
 148
 149    /* From the Graphics BSpec: vol5c Shared Functions [SNB+] > State >
 150     * SURFACE_STATE > SURFACE_STATE for most messages [DevIVB]: Surface Array
 151     * Spacing:
 152     *
 153     *   If Multisampled Surface Storage Format is MSFMT_MSS and Number of
 154     *   Multisamples is not MULTISAMPLECOUNT_1, this field must be set to
 155     *   ARYSPC_LOD0.
 156     */
 157    if (multisampled_surface_storage_format == GEN7_SURFACE_MSFMT_MSS
 158        && is_multisampled)
 159       assert(surface_array_spacing == GEN7_SURFACE_ARYSPC_LOD0);
 160
 161    /* From the Graphics BSpec: vol5c Shared Functions [SNB+] > State >
 162     * SURFACE_STATE > SURFACE_STATE for most messages [DevIVB]: Multisampled
 163     * Surface Storage Format:
 164     *
 165     *   All multisampled render target surfaces must have this field set to
 166     *   MSFMT_MSS.
 167     *
 168     * But also:
 169     *
 170     *   This field is ignored if Number of Multisamples is MULTISAMPLECOUNT_1.
 171     */
 172    if (is_render_target && is_multisampled) {
 173       assert(multisampled_surface_storage_format == GEN7_SURFACE_MSFMT_MSS);
 174    }
 175
 176    /* From the Graphics BSpec: vol5c Shared Functions [SNB+] > State >
 177     * SURFACE_STATE > SURFACE_STATE for most messages [DevIVB]: Multisampled
 178     * Surface Storage Format:
 179     *
 180     *   If the surface’s Number of Multisamples is MULTISAMPLECOUNT_8, Width
 181     *   is >= 8192 (meaning the actual surface width is >= 8193 pixels), this
 182     *   field must be set to MSFMT_MSS.
 183     */
 184    uint32_t width = GET_FIELD(surf[2], GEN7_SURFACE_WIDTH) + 1;
 185    if (num_multisamples == GEN7_SURFACE_MULTISAMPLECOUNT_8 && width >= 8193) {
 186       assert(multisampled_surface_storage_format == GEN7_SURFACE_MSFMT_MSS);
 187    }
 188
 189    /* From the Graphics BSpec: vol5c Shared Functions [SNB+] > State >
 190     * SURFACE_STATE > SURFACE_STATE for most messages [DevIVB]: Multisampled
 191     * Surface Storage Format:
 192     *
 193     *   If the surface’s Number of Multisamples is MULTISAMPLECOUNT_8,
 194     *   ((Depth+1) * (Height+1)) is > 4,194,304, OR if the surface’s Number of
 195     *   Multisamples is MULTISAMPLECOUNT_4, ((Depth+1) * (Height+1)) is >
 196     *   8,388,608, this field must be set to MSFMT_DEPTH_STENCIL.This field
 197     *   must be set to MSFMT_DEPTH_STENCIL if Surface Format is one of the
 198     *   following: I24X8_UNORM, L24X8_UNORM, A24X8_UNORM, or
 199     *   R24_UNORM_X8_TYPELESS.
 200     *
 201     * But also:
 202     *
 203     *   This field is ignored if Number of Multisamples is MULTISAMPLECOUNT_1.
 204     */
 205    uint32_t depth = GET_FIELD(surf[3], BRW_SURFACE_DEPTH) + 1;
 206    uint32_t height = GET_FIELD(surf[2], GEN7_SURFACE_HEIGHT) + 1;
 207    if (num_multisamples == GEN7_SURFACE_MULTISAMPLECOUNT_8 &&
 208        depth * height > 4194304) {
 209       assert(multisampled_surface_storage_format ==
 210              GEN7_SURFACE_MSFMT_DEPTH_STENCIL);
 211    }
 212    if (num_multisamples == GEN7_SURFACE_MULTISAMPLECOUNT_4 &&
 213        depth * height > 8388608) {
 214       assert(multisampled_surface_storage_format ==
 215              GEN7_SURFACE_MSFMT_DEPTH_STENCIL);
 216    }
 217    if (is_multisampled) {
 218       switch (GET_FIELD(surf[0], BRW_SURFACE_FORMAT)) {
 219       case BRW_SURFACEFORMAT_I24X8_UNORM:
 220       case BRW_SURFACEFORMAT_L24X8_UNORM:
 221       case BRW_SURFACEFORMAT_A24X8_UNORM:
 222       case BRW_SURFACEFORMAT_R24_UNORM_X8_TYPELESS:
 223          assert(multisampled_surface_storage_format ==
 224                 GEN7_SURFACE_MSFMT_DEPTH_STENCIL);
 225       }
 226    }
 227 }
 228
 229
 230 static void
 231 gen7_update_buffer_texture_surface(struct gl_context *ctx,
 232                                    unsigned unit,
 233                                    uint32_t *binding_table,
 234                                    unsigned surf_index)
 235 {
 236    struct brw_context *brw = brw_context(ctx);
 237    struct intel_context *intel = &brw->intel;
 238    struct gl_texture_object *tObj = ctx->Texture.Unit[unit]._Current;
 239    struct intel_buffer_object *intel_obj =
 240       intel_buffer_object(tObj->BufferObject);
 241    drm_intel_bo *bo = intel_obj ? intel_obj->buffer : NULL;
 242    gl_format format = tObj->_BufferObjectFormat;
 243
 244    uint32_t *surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE,
 245                                     8 * 4, 32, &binding_table[surf_index]);
 246    memset(surf, 0, 8 * 4);
 247
 248    uint32_t surface_format = brw_format_for_mesa_format(format);
 249    if (surface_format == 0 && format != MESA_FORMAT_RGBA_FLOAT32) {
 250       _mesa_problem(NULL, "bad format %s for texture buffer\n",
 251                     _mesa_get_format_name(format));
 252    }
 253
 254    surf[0] = BRW_SURFACE_BUFFER << BRW_SURFACE_TYPE_SHIFT |
 255              surface_format << BRW_SURFACE_FORMAT_SHIFT |
 256              BRW_SURFACE_RC_READ_WRITE;
 257
 258    if (bo) {
 259       surf[1] = bo->offset; /* reloc */
 260
 261       /* Emit relocation to surface contents.  Section 5.1.1 of the gen4
 262        * bspec ("Data Cache") says that the data cache does not exist as
 263        * a separate cache and is just the sampler cache.
 264        */
 265       drm_intel_bo_emit_reloc(intel->batch.bo,
 266                               binding_table[surf_index] + 4,
 267                               bo, 0,
 268                               I915_GEM_DOMAIN_SAMPLER, 0);
 269
 270       int texel_size = _mesa_get_format_bytes(format);
 271       int w = intel_obj->Base.Size / texel_size;
 272       surf[2] = SET_FIELD(w & 0x7f, GEN7_SURFACE_WIDTH) | /* bits 6:0 of size */
 273                 SET_FIELD((w >> 7) & 0x1fff, GEN7_SURFACE_HEIGHT); /* 19:7 */
 274       surf[3] = SET_FIELD((w >> 20) & 0x7f, BRW_SURFACE_DEPTH) | /* bits 26:20 */
 275                 (texel_size - 1);
 276    }
 277
 278    gen7_check_surface_setup(surf, false /* is_render_target */);
 279 }
 280
 281 static void
 282 gen7_update_texture_surface(struct gl_context *ctx,
 283                             unsigned unit,
 284                             uint32_t *binding_table,
 285                             unsigned surf_index)
 286 {
 287    struct brw_context *brw = brw_context(ctx);
 288    struct intel_context *intel = &brw->intel;
 289    struct gl_texture_object *tObj = ctx->Texture.Unit[unit]._Current;
 290    struct intel_texture_object *intelObj = intel_texture_object(tObj);
 291    struct intel_mipmap_tree *mt = intelObj->mt;
 292    struct gl_texture_image *firstImage = tObj->Image[0][tObj->BaseLevel];
 293    struct gl_sampler_object *sampler = _mesa_get_samplerobj(ctx, unit);
 294    int width, height, depth;
 295    uint32_t tile_x, tile_y;
 296
 297    if (tObj->Target == GL_TEXTURE_BUFFER) {
 298       gen7_update_buffer_texture_surface(ctx, unit, binding_table, surf_index);
 299       return;
 300    }
 301
 302    intel_miptree_get_dimensions_for_image(firstImage, &width, &height, &depth);
 303
 304    uint32_t *surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE,
 305                                     8 * 4, 32, &binding_table[surf_index]);
 306    memset(surf, 0, 8 * 4);
 307
 308    uint32_t tex_format = translate_tex_format(intel,
 309                                               mt->format,
 310                                               firstImage->InternalFormat,
 311                                               tObj->DepthMode,
 312                                               sampler->sRGBDecode);
 313
 314    surf[0] = translate_tex_target(tObj->Target) << BRW_SURFACE_TYPE_SHIFT |
 315              tex_format << BRW_SURFACE_FORMAT_SHIFT |
 316              gen7_surface_tiling_mode(mt->region->tiling) |
 317              BRW_SURFACE_CUBEFACE_ENABLES;
 318
 319    if (mt->align_h == 4)
 320       surf[0] |= GEN7_SURFACE_VALIGN_4;
 321    if (mt->align_w == 8)
 322       surf[0] |= GEN7_SURFACE_HALIGN_8;
 323
 324    if (depth > 1 && tObj->Target != GL_TEXTURE_3D)
 325       surf[0] |= GEN7_SURFACE_IS_ARRAY;
 326
 327    if (mt->array_spacing_lod0)
 328       surf[0] |= GEN7_SURFACE_ARYSPC_LOD0;
 329
 330    surf[1] = mt->region->bo->offset + mt->offset; /* reloc */
 331
 332    surf[2] = SET_FIELD(width - 1, GEN7_SURFACE_WIDTH) |
 333              SET_FIELD(height - 1, GEN7_SURFACE_HEIGHT);
 334    surf[3] = SET_FIELD(depth - 1, BRW_SURFACE_DEPTH) |
 335              ((intelObj->mt->region->pitch) - 1);
 336
 337    surf[4] = gen7_surface_msaa_bits(mt->num_samples, mt->msaa_layout);
 338
 339    intel_miptree_get_tile_offsets(intelObj->mt, firstImage->Level, 0,
 340                                   &tile_x, &tile_y);
 341    assert(brw->has_surface_tile_offset || (tile_x == 0 && tile_y == 0));
 342    /* Note that the low bits of these fields are missing, so
 343     * there's the possibility of getting in trouble.
 344     */
 345    surf[5] = ((tile_x / 4) << BRW_SURFACE_X_OFFSET_SHIFT |
 346               (tile_y / 2) << BRW_SURFACE_Y_OFFSET_SHIFT |
 347               /* mip count */
 348               (intelObj->_MaxLevel - tObj->BaseLevel));
 349
 350    if (intel->is_haswell) {
 351       /* Handling GL_ALPHA as a surface format override breaks 1.30+ style
 352        * texturing functions that return a float, as our code generation always
 353        * selects the .x channel (which would always be 0).
 354        */
 355       const bool alpha_depth = tObj->DepthMode == GL_ALPHA &&
 356          (firstImage->_BaseFormat == GL_DEPTH_COMPONENT ||
 357           firstImage->_BaseFormat == GL_DEPTH_STENCIL);
 358
 359       const int swizzle = unlikely(alpha_depth)
 360          ? SWIZZLE_XYZW : brw_get_texture_swizzle(ctx, tObj);
 361
 362       surf[7] =
 363          SET_FIELD(swizzle_to_scs(GET_SWZ(swizzle, 0)), GEN7_SURFACE_SCS_R) |
 364          SET_FIELD(swizzle_to_scs(GET_SWZ(swizzle, 1)), GEN7_SURFACE_SCS_G) |
 365          SET_FIELD(swizzle_to_scs(GET_SWZ(swizzle, 2)), GEN7_SURFACE_SCS_B) |
 366          SET_FIELD(swizzle_to_scs(GET_SWZ(swizzle, 3)), GEN7_SURFACE_SCS_A);
 367    }
 368
 369    /* Emit relocation to surface contents */
 370    drm_intel_bo_emit_reloc(brw->intel.batch.bo,
 371                            binding_table[surf_index] + 4,
 372                            intelObj->mt->region->bo, intelObj->mt->offset,
 373                            I915_GEM_DOMAIN_SAMPLER, 0);
 374
 375    gen7_check_surface_setup(surf, false /* is_render_target */);
 376 }
 377
 378 /**
 379  * Create the constant buffer surface.  Vertex/fragment shader constants will
 380  * be read from this buffer with Data Port Read instructions/messages.
 381  */
 382 static void
 383 gen7_create_constant_surface(struct brw_context *brw,
 384                              drm_intel_bo *bo,
 385                              uint32_t offset,
 386                              int width,
 387                              uint32_t *out_offset)
 388 {
 389    struct intel_context *intel = &brw->intel;
 390    const GLint w = width - 1;
 391
 392    uint32_t *surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE,
 393                                     8 * 4, 32, out_offset);
 394    memset(surf, 0, 8 * 4);
 395
 396    surf[0] = BRW_SURFACE_BUFFER << BRW_SURFACE_TYPE_SHIFT |
 397              BRW_SURFACEFORMAT_R32G32B32A32_FLOAT << BRW_SURFACE_FORMAT_SHIFT |
 398              BRW_SURFACE_RC_READ_WRITE;
 399
 400    assert(bo);
 401    surf[1] = bo->offset + offset; /* reloc */
 402
 403    surf[2] = SET_FIELD(w & 0x7f, GEN7_SURFACE_WIDTH) |
 404              SET_FIELD((w >> 7) & 0x1fff, GEN7_SURFACE_HEIGHT);
 405    surf[3] = SET_FIELD((w >> 20) & 0x7f, BRW_SURFACE_DEPTH) |
 406              (16 - 1); /* stride between samples */
 407
 408    if (intel->is_haswell) {
 409       surf[7] = SET_FIELD(HSW_SCS_RED,   GEN7_SURFACE_SCS_R) |
 410                 SET_FIELD(HSW_SCS_GREEN, GEN7_SURFACE_SCS_G) |
 411                 SET_FIELD(HSW_SCS_BLUE,  GEN7_SURFACE_SCS_B) |
 412                 SET_FIELD(HSW_SCS_ALPHA, GEN7_SURFACE_SCS_A);
 413    }
 414
 415    /* Emit relocation to surface contents.  Section 5.1.1 of the gen4
 416     * bspec ("Data Cache") says that the data cache does not exist as
 417     * a separate cache and is just the sampler cache.
 418     */
 419    drm_intel_bo_emit_reloc(intel->batch.bo,
 420                            *out_offset + 4,
 421                            bo, offset,
 422                            I915_GEM_DOMAIN_SAMPLER, 0);
 423
 424    gen7_check_surface_setup(surf, false /* is_render_target */);
 425 }
 426
 427 static void
 428 gen7_update_null_renderbuffer_surface(struct brw_context *brw, unsigned unit)
 429 {
 430    /* From the Ivy bridge PRM, Vol4 Part1 p62 (Surface Type: Programming
 431     * Notes):
 432     *
 433     *     A null surface is used in instances where an actual surface is not
 434     *     bound. When a write message is generated to a null surface, no
 435     *     actual surface is written to. When a read message (including any
 436     *     sampling engine message) is generated to a null surface, the result
 437     *     is all zeros. Note that a null surface type is allowed to be used
 438     *     with all messages, even if it is not specificially indicated as
 439     *     supported. All of the remaining fields in surface state are ignored
 440     *     for null surfaces, with the following exceptions: Width, Height,
 441     *     Depth, LOD, and Render Target View Extent fields must match the
 442     *     depth buffer’s corresponding state for all render target surfaces,
 443     *     including null.
 444     */
 445    struct intel_context *intel = &brw->intel;
 446    struct gl_context *ctx = &intel->ctx;
 447
 448    /* _NEW_BUFFERS */
 449    const struct gl_framebuffer *fb = ctx->DrawBuffer;
 450
 451    uint32_t *surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE,
 452                                     8 * 4, 32, &brw->wm.surf_offset[unit]);
 453    memset(surf, 0, 8 * 4);
 454
 455    /* From the Ivybridge PRM, Volume 4, Part 1, page 65,
 456     * Tiled Surface: Programming Notes:
 457     * "If Surface Type is SURFTYPE_NULL, this field must be TRUE."
 458     */
 459    surf[0] = BRW_SURFACE_NULL << BRW_SURFACE_TYPE_SHIFT |
 460              BRW_SURFACEFORMAT_B8G8R8A8_UNORM << BRW_SURFACE_FORMAT_SHIFT |
 461              GEN7_SURFACE_TILING_Y;
 462
 463    surf[2] = SET_FIELD(fb->Width - 1, GEN7_SURFACE_WIDTH) |
 464              SET_FIELD(fb->Height - 1, GEN7_SURFACE_HEIGHT);
 465
 466    gen7_check_surface_setup(surf, true /* is_render_target */);
 467 }
 468
 469 /**
 470  * Sets up a surface state structure to point at the given region.
 471  * While it is only used for the front/back buffer currently, it should be
 472  * usable for further buffers when doing ARB_draw_buffer support.
 473  */
 474 static void
 475 gen7_update_renderbuffer_surface(struct brw_context *brw,
 476                                  struct gl_renderbuffer *rb,
 477                                  unsigned int unit)
 478 {
 479    struct intel_context *intel = &brw->intel;
 480    struct gl_context *ctx = &intel->ctx;
 481    struct intel_renderbuffer *irb = intel_renderbuffer(rb);
 482    struct intel_region *region = irb->mt->region;
 483    uint32_t tile_x, tile_y;
 484    uint32_t format;
 485    gl_format rb_format = intel_rb_format(irb);
 486
 487    uint32_t *surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE,
 488                                     8 * 4, 32, &brw->wm.surf_offset[unit]);
 489    memset(surf, 0, 8 * 4);
 490
 491    /* Render targets can't use IMS layout */
 492    assert(irb->mt->msaa_layout != INTEL_MSAA_LAYOUT_IMS);
 493
 494    switch (rb_format) {
 495    case MESA_FORMAT_SARGB8:
 496       /* _NEW_BUFFERS
 497        *
 498        * Without GL_EXT_framebuffer_sRGB we shouldn't bind sRGB surfaces to the
 499        * blend/update as sRGB.
 500        */
 501       if (ctx->Color.sRGBEnabled)
 502          format = brw_format_for_mesa_format(rb_format);
 503       else
 504          format = BRW_SURFACEFORMAT_B8G8R8A8_UNORM;
 505       break;
 506    default:
 507       assert(brw_render_target_supported(intel, rb));
 508       format = brw->render_target_format[rb_format];
 509       if (unlikely(!brw->format_supported_as_render_target[rb_format])) {
 510          _mesa_problem(ctx, "%s: renderbuffer format %s unsupported\n",
 511                        __FUNCTION__, _mesa_get_format_name(rb_format));
 512       }
 513       break;
 514    }
 515
 516    surf[0] = BRW_SURFACE_2D << BRW_SURFACE_TYPE_SHIFT |
 517              format << BRW_SURFACE_FORMAT_SHIFT |
 518              (irb->mt->array_spacing_lod0 ? GEN7_SURFACE_ARYSPC_LOD0
 519                                           : GEN7_SURFACE_ARYSPC_FULL) |
 520              gen7_surface_tiling_mode(region->tiling);
 521
 522    if (irb->mt->align_h == 4)
 523       surf[0] |= GEN7_SURFACE_VALIGN_4;
 524    if (irb->mt->align_w == 8)
 525       surf[0] |= GEN7_SURFACE_HALIGN_8;
 526
 527    /* reloc */
 528    surf[1] = intel_renderbuffer_tile_offsets(irb, &tile_x, &tile_y) +
 529              region->bo->offset; /* reloc */
 530
 531    assert(brw->has_surface_tile_offset);
 532    /* Note that the low bits of these fields are missing, so
 533     * there's the possibility of getting in trouble.
 534     */
 535    assert(tile_x % 4 == 0);
 536    assert(tile_y % 2 == 0);
 537    surf[5] = SET_FIELD(tile_x / 4, BRW_SURFACE_X_OFFSET) |
 538              SET_FIELD(tile_y / 2, BRW_SURFACE_Y_OFFSET);
 539
 540    surf[2] = SET_FIELD(rb->Width - 1, GEN7_SURFACE_WIDTH) |
 541              SET_FIELD(rb->Height - 1, GEN7_SURFACE_HEIGHT);
 542    surf[3] = region->pitch - 1;
 543
 544    surf[4] = gen7_surface_msaa_bits(irb->mt->num_samples, irb->mt->msaa_layout);
 545
 546    if (irb->mt->msaa_layout == INTEL_MSAA_LAYOUT_CMS) {
 547       gen7_set_surface_mcs_info(brw, surf, brw->wm.surf_offset[unit],
 548                                 irb->mt->mcs_mt, true /* is RT */);
 549    }
 550
 551    if (intel->is_haswell) {
 552       surf[7] = SET_FIELD(HSW_SCS_RED,   GEN7_SURFACE_SCS_R) |
 553                 SET_FIELD(HSW_SCS_GREEN, GEN7_SURFACE_SCS_G) |
 554                 SET_FIELD(HSW_SCS_BLUE,  GEN7_SURFACE_SCS_B) |
 555                 SET_FIELD(HSW_SCS_ALPHA, GEN7_SURFACE_SCS_A);
 556    }
 557
 558    drm_intel_bo_emit_reloc(brw->intel.batch.bo,
 559                            brw->wm.surf_offset[unit] + 4,
 560                            region->bo,
 561                            surf[1] - region->bo->offset,
 562                            I915_GEM_DOMAIN_RENDER,
 563                            I915_GEM_DOMAIN_RENDER);
 564
 565    gen7_check_surface_setup(surf, true /* is_render_target */);
 566 }
 567
 568 void
 569 gen7_init_vtable_surface_functions(struct brw_context *brw)
 570 {
 571    struct intel_context *intel = &brw->intel;
 572
 573    intel->vtbl.update_texture_surface = gen7_update_texture_surface;
 574    intel->vtbl.update_renderbuffer_surface = gen7_update_renderbuffer_surface;
 575    intel->vtbl.update_null_renderbuffer_surface =
 576       gen7_update_null_renderbuffer_surface;
 577    intel->vtbl.create_constant_surface = gen7_create_constant_surface;
 578 }