src/mesa/drivers/dri/i965/gen7_wm_surface_state.c

   1 /*
   2  * Copyright © 2011 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23 #include "main/mtypes.h"
  24 #include "main/blend.h"
  25 #include "main/samplerobj.h"
  26 #include "main/texformat.h"
  27 #include "program/prog_parameter.h"
  28
  29 #include "intel_mipmap_tree.h"
  30 #include "intel_batchbuffer.h"
  31 #include "intel_tex.h"
  32 #include "intel_fbo.h"
  33 #include "intel_buffer_objects.h"
  34
  35 #include "brw_context.h"
  36 #include "brw_state.h"
  37 #include "brw_defines.h"
  38 #include "brw_wm.h"
  39
  40 /**
  41  * Convert an swizzle enumeration (i.e. SWIZZLE_X) to one of the Gen7.5+
  42  * "Shader Channel Select" enumerations (i.e. HSW_SCS_RED)
  43  */
  44 unsigned
  45 brw_swizzle_to_scs(GLenum swizzle, bool need_green_to_blue)
  46 {
  47    switch (swizzle) {
  48    case SWIZZLE_X:
  49       return HSW_SCS_RED;
  50    case SWIZZLE_Y:
  51       return need_green_to_blue ? HSW_SCS_BLUE : HSW_SCS_GREEN;
  52    case SWIZZLE_Z:
  53       return HSW_SCS_BLUE;
  54    case SWIZZLE_W:
  55       return HSW_SCS_ALPHA;
  56    case SWIZZLE_ZERO:
  57       return HSW_SCS_ZERO;
  58    case SWIZZLE_ONE:
  59       return HSW_SCS_ONE;
  60    }
  61
  62    assert(!"Should not get here: invalid swizzle mode");
  63    return HSW_SCS_ZERO;
  64 }
  65
  66 uint32_t
  67 gen7_surface_tiling_mode(uint32_t tiling)
  68 {
  69    switch (tiling) {
  70    case I915_TILING_X:
  71       return GEN7_SURFACE_TILING_X;
  72    case I915_TILING_Y:
  73       return GEN7_SURFACE_TILING_Y;
  74    default:
  75       return GEN7_SURFACE_TILING_NONE;
  76    }
  77 }
  78
  79
  80 uint32_t
  81 gen7_surface_msaa_bits(unsigned num_samples, enum intel_msaa_layout layout)
  82 {
  83    uint32_t ss4 = 0;
  84
  85    if (num_samples > 4)
  86       ss4 |= GEN7_SURFACE_MULTISAMPLECOUNT_8;
  87    else if (num_samples > 1)
  88       ss4 |= GEN7_SURFACE_MULTISAMPLECOUNT_4;
  89    else
  90       ss4 |= GEN7_SURFACE_MULTISAMPLECOUNT_1;
  91
  92    if (layout == INTEL_MSAA_LAYOUT_IMS)
  93       ss4 |= GEN7_SURFACE_MSFMT_DEPTH_STENCIL;
  94    else
  95       ss4 |= GEN7_SURFACE_MSFMT_MSS;
  96
  97    return ss4;
  98 }
  99
 100
 101 void
 102 gen7_set_surface_mcs_info(struct brw_context *brw,
 103                           uint32_t *surf,
 104                           uint32_t surf_offset,
 105                           const struct intel_mipmap_tree *mcs_mt,
 106                           bool is_render_target)
 107 {
 108    /* From the Ivy Bridge PRM, Vol4 Part1 p76, "MCS Base Address":
 109     *
 110     *     "The MCS surface must be stored as Tile Y."
 111     */
 112    assert(mcs_mt->region->tiling == I915_TILING_Y);
 113
 114    /* Compute the pitch in units of tiles.  To do this we need to divide the
 115     * pitch in bytes by 128, since a single Y-tile is 128 bytes wide.
 116     */
 117    unsigned pitch_tiles = mcs_mt->region->pitch / 128;
 118
 119    /* The upper 20 bits of surface state DWORD 6 are the upper 20 bits of the
 120     * GPU address of the MCS buffer; the lower 12 bits contain other control
 121     * information.  Since buffer addresses are always on 4k boundaries (and
 122     * thus have their lower 12 bits zero), we can use an ordinary reloc to do
 123     * the necessary address translation.
 124     */
 125    assert ((mcs_mt->region->bo->offset64 & 0xfff) == 0);
 126
 127    surf[6] = GEN7_SURFACE_MCS_ENABLE |
 128              SET_FIELD(pitch_tiles - 1, GEN7_SURFACE_MCS_PITCH) |
 129              mcs_mt->region->bo->offset64;
 130
 131    drm_intel_bo_emit_reloc(brw->batch.bo,
 132                            surf_offset + 6 * 4,
 133                            mcs_mt->region->bo,
 134                            surf[6] & 0xfff,
 135                            is_render_target ? I915_GEM_DOMAIN_RENDER
 136                            : I915_GEM_DOMAIN_SAMPLER,
 137                            is_render_target ? I915_GEM_DOMAIN_RENDER : 0);
 138 }
 139
 140
 141 void
 142 gen7_check_surface_setup(uint32_t *surf, bool is_render_target)
 143 {
 144    unsigned num_multisamples = surf[4] & INTEL_MASK(5, 3);
 145    unsigned multisampled_surface_storage_format = surf[4] & (1 << 6);
 146    unsigned surface_array_spacing = surf[0] & (1 << 10);
 147    bool is_multisampled = num_multisamples != GEN7_SURFACE_MULTISAMPLECOUNT_1;
 148
 149    (void) surface_array_spacing;
 150
 151    /* From the Ivybridge PRM, Volume 4 Part 1, page 66 (RENDER_SURFACE_STATE
 152     * dword 0 bit 10 "Surface Array Spacing" Programming Notes):
 153     *
 154     *   If Multisampled Surface Storage Format is MSFMT_MSS and Number of
 155     *   Multisamples is not MULTISAMPLECOUNT_1, this field must be set to
 156     *   ARYSPC_LOD0.
 157     */
 158    if (multisampled_surface_storage_format == GEN7_SURFACE_MSFMT_MSS
 159        && is_multisampled)
 160       assert(surface_array_spacing == GEN7_SURFACE_ARYSPC_LOD0);
 161
 162    /* From the Ivybridge PRM, Volume 4 Part 1, page 72 (RENDER_SURFACE_STATE
 163     * dword 4 bit 6 "Multisampled Surface Storage" Programming Notes):
 164     *
 165     *   All multisampled render target surfaces must have this field set to
 166     *   MSFMT_MSS.
 167     *
 168     * But also:
 169     *
 170     *   This field is ignored if Number of Multisamples is MULTISAMPLECOUNT_1.
 171     */
 172    if (is_render_target && is_multisampled) {
 173       assert(multisampled_surface_storage_format == GEN7_SURFACE_MSFMT_MSS);
 174    }
 175
 176    /* From the Ivybridge PRM, Volume 4 Part 1, page 72 (RENDER_SURFACE_STATE
 177     * dword 4 bit 6 "Multisampled Surface Storage Format" Errata):
 178     *
 179     *   If the surface’s Number of Multisamples is MULTISAMPLECOUNT_8, Width
 180     *   is >= 8192 (meaning the actual surface width is >= 8193 pixels), this
 181     *   field must be set to MSFMT_MSS.
 182     */
 183    uint32_t width = GET_FIELD(surf[2], GEN7_SURFACE_WIDTH) + 1;
 184    if (num_multisamples == GEN7_SURFACE_MULTISAMPLECOUNT_8 && width >= 8193) {
 185       assert(multisampled_surface_storage_format == GEN7_SURFACE_MSFMT_MSS);
 186    }
 187
 188    /* From the Ivybridge PRM, Volume 4 Part 1, page 72 (RENDER_SURFACE_STATE
 189     * dword 4 bit 6 "Multisampled Surface Storage Format" Errata):
 190     *
 191     *   If the surface’s Number of Multisamples is MULTISAMPLECOUNT_8,
 192     *   ((Depth+1) * (Height+1)) is > 4,194,304, OR if the surface’s Number of
 193     *   Multisamples is MULTISAMPLECOUNT_4, ((Depth+1) * (Height+1)) is >
 194     *   8,388,608, this field must be set to MSFMT_DEPTH_STENCIL.This field
 195     *   must be set to MSFMT_DEPTH_STENCIL if Surface Format is one of the
 196     *   following: I24X8_UNORM, L24X8_UNORM, A24X8_UNORM, or
 197     *   R24_UNORM_X8_TYPELESS.
 198     *
 199     * But also (from the Programming Notes):
 200     *
 201     *   This field is ignored if Number of Multisamples is MULTISAMPLECOUNT_1.
 202     */
 203    uint32_t depth = GET_FIELD(surf[3], BRW_SURFACE_DEPTH) + 1;
 204    uint32_t height = GET_FIELD(surf[2], GEN7_SURFACE_HEIGHT) + 1;
 205    if (num_multisamples == GEN7_SURFACE_MULTISAMPLECOUNT_8 &&
 206        depth * height > 4194304) {
 207       assert(multisampled_surface_storage_format ==
 208              GEN7_SURFACE_MSFMT_DEPTH_STENCIL);
 209    }
 210    if (num_multisamples == GEN7_SURFACE_MULTISAMPLECOUNT_4 &&
 211        depth * height > 8388608) {
 212       assert(multisampled_surface_storage_format ==
 213              GEN7_SURFACE_MSFMT_DEPTH_STENCIL);
 214    }
 215    if (is_multisampled) {
 216       switch (GET_FIELD(surf[0], BRW_SURFACE_FORMAT)) {
 217       case BRW_SURFACEFORMAT_I24X8_UNORM:
 218       case BRW_SURFACEFORMAT_L24X8_UNORM:
 219       case BRW_SURFACEFORMAT_A24X8_UNORM:
 220       case BRW_SURFACEFORMAT_R24_UNORM_X8_TYPELESS:
 221          assert(multisampled_surface_storage_format ==
 222                 GEN7_SURFACE_MSFMT_DEPTH_STENCIL);
 223       }
 224    }
 225 }
 226
 227 static void
 228 gen7_emit_buffer_surface_state(struct brw_context *brw,
 229                                uint32_t *out_offset,
 230                                drm_intel_bo *bo,
 231                                unsigned buffer_offset,
 232                                unsigned surface_format,
 233                                unsigned buffer_size,
 234                                unsigned pitch,
 235                                unsigned mocs,
 236                                bool rw)
 237 {
 238    uint32_t *surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE,
 239                                     8 * 4, 32, out_offset);
 240    memset(surf, 0, 8 * 4);
 241
 242    surf[0] = BRW_SURFACE_BUFFER << BRW_SURFACE_TYPE_SHIFT |
 243              surface_format << BRW_SURFACE_FORMAT_SHIFT |
 244              BRW_SURFACE_RC_READ_WRITE;
 245    surf[1] = (bo ? bo->offset64 : 0) + buffer_offset; /* reloc */
 246    surf[2] = SET_FIELD((buffer_size - 1) & 0x7f, GEN7_SURFACE_WIDTH) |
 247              SET_FIELD(((buffer_size - 1) >> 7) & 0x3fff, GEN7_SURFACE_HEIGHT);
 248    surf[3] = SET_FIELD(((buffer_size - 1) >> 21) & 0x3f, BRW_SURFACE_DEPTH) |
 249              (pitch - 1);
 250
 251    surf[5] = SET_FIELD(mocs, GEN7_SURFACE_MOCS);
 252
 253    if (brw->is_haswell) {
 254       surf[7] |= (SET_FIELD(HSW_SCS_RED,   GEN7_SURFACE_SCS_R) |
 255                   SET_FIELD(HSW_SCS_GREEN, GEN7_SURFACE_SCS_G) |
 256                   SET_FIELD(HSW_SCS_BLUE,  GEN7_SURFACE_SCS_B) |
 257                   SET_FIELD(HSW_SCS_ALPHA, GEN7_SURFACE_SCS_A));
 258    }
 259
 260    /* Emit relocation to surface contents */
 261    if (bo) {
 262       drm_intel_bo_emit_reloc(brw->batch.bo, *out_offset + 4,
 263                               bo, buffer_offset, I915_GEM_DOMAIN_SAMPLER,
 264                               (rw ? I915_GEM_DOMAIN_SAMPLER : 0));
 265    }
 266
 267    gen7_check_surface_setup(surf, false /* is_render_target */);
 268 }
 269
 270 static void
 271 gen7_update_texture_surface(struct gl_context *ctx,
 272                             unsigned unit,
 273                             uint32_t *surf_offset,
 274                             bool for_gather)
 275 {
 276    struct brw_context *brw = brw_context(ctx);
 277    struct gl_texture_object *tObj = ctx->Texture.Unit[unit]._Current;
 278    struct intel_texture_object *intelObj = intel_texture_object(tObj);
 279    struct intel_mipmap_tree *mt = intelObj->mt;
 280    struct gl_texture_image *firstImage = tObj->Image[0][tObj->BaseLevel];
 281    struct gl_sampler_object *sampler = _mesa_get_samplerobj(ctx, unit);
 282
 283    if (tObj->Target == GL_TEXTURE_BUFFER) {
 284       brw_update_buffer_texture_surface(ctx, unit, surf_offset);
 285       return;
 286    }
 287
 288    uint32_t *surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE,
 289                                     8 * 4, 32, surf_offset);
 290    memset(surf, 0, 8 * 4);
 291
 292    uint32_t tex_format = translate_tex_format(brw,
 293                                               mt->format,
 294                                               sampler->sRGBDecode);
 295
 296    if (for_gather && tex_format == BRW_SURFACEFORMAT_R32G32_FLOAT)
 297       tex_format = BRW_SURFACEFORMAT_R32G32_FLOAT_LD;
 298
 299    surf[0] = translate_tex_target(tObj->Target) << BRW_SURFACE_TYPE_SHIFT |
 300              tex_format << BRW_SURFACE_FORMAT_SHIFT |
 301              gen7_surface_tiling_mode(mt->region->tiling);
 302
 303    /* mask of faces present in cube map; for other surfaces MBZ. */
 304    if (tObj->Target == GL_TEXTURE_CUBE_MAP || tObj->Target == GL_TEXTURE_CUBE_MAP_ARRAY)
 305       surf[0] |= BRW_SURFACE_CUBEFACE_ENABLES;
 306
 307    if (mt->align_h == 4)
 308       surf[0] |= GEN7_SURFACE_VALIGN_4;
 309    if (mt->align_w == 8)
 310       surf[0] |= GEN7_SURFACE_HALIGN_8;
 311
 312    if (mt->logical_depth0 > 1 && tObj->Target != GL_TEXTURE_3D)
 313       surf[0] |= GEN7_SURFACE_IS_ARRAY;
 314
 315    if (mt->array_spacing_lod0)
 316       surf[0] |= GEN7_SURFACE_ARYSPC_LOD0;
 317
 318    surf[1] = mt->region->bo->offset64 + mt->offset; /* reloc */
 319
 320    surf[2] = SET_FIELD(mt->logical_width0 - 1, GEN7_SURFACE_WIDTH) |
 321              SET_FIELD(mt->logical_height0 - 1, GEN7_SURFACE_HEIGHT);
 322    surf[3] = SET_FIELD(mt->logical_depth0 - 1, BRW_SURFACE_DEPTH) |
 323              ((intelObj->mt->region->pitch) - 1);
 324
 325    surf[4] = gen7_surface_msaa_bits(mt->num_samples, mt->msaa_layout);
 326
 327    surf[5] = (SET_FIELD(GEN7_MOCS_L3, GEN7_SURFACE_MOCS) |
 328               SET_FIELD(tObj->BaseLevel - mt->first_level,
 329                         GEN7_SURFACE_MIN_LOD) |
 330               /* mip count */
 331               (intelObj->_MaxLevel - tObj->BaseLevel));
 332
 333    if (brw->is_haswell) {
 334       /* Handling GL_ALPHA as a surface format override breaks 1.30+ style
 335        * texturing functions that return a float, as our code generation always
 336        * selects the .x channel (which would always be 0).
 337        */
 338       const bool alpha_depth = tObj->DepthMode == GL_ALPHA &&
 339          (firstImage->_BaseFormat == GL_DEPTH_COMPONENT ||
 340           firstImage->_BaseFormat == GL_DEPTH_STENCIL);
 341
 342       const int swizzle = unlikely(alpha_depth)
 343          ? SWIZZLE_XYZW : brw_get_texture_swizzle(ctx, tObj);
 344
 345       const bool need_scs_green_to_blue = for_gather && tex_format == BRW_SURFACEFORMAT_R32G32_FLOAT_LD;
 346
 347       surf[7] =
 348          SET_FIELD(brw_swizzle_to_scs(GET_SWZ(swizzle, 0), need_scs_green_to_blue), GEN7_SURFACE_SCS_R) |
 349          SET_FIELD(brw_swizzle_to_scs(GET_SWZ(swizzle, 1), need_scs_green_to_blue), GEN7_SURFACE_SCS_G) |
 350          SET_FIELD(brw_swizzle_to_scs(GET_SWZ(swizzle, 2), need_scs_green_to_blue), GEN7_SURFACE_SCS_B) |
 351          SET_FIELD(brw_swizzle_to_scs(GET_SWZ(swizzle, 3), need_scs_green_to_blue), GEN7_SURFACE_SCS_A);
 352    }
 353
 354    if (mt->mcs_mt) {
 355       gen7_set_surface_mcs_info(brw, surf, *surf_offset,
 356                                 mt->mcs_mt, false /* is RT */);
 357    }
 358
 359    /* Emit relocation to surface contents */
 360    drm_intel_bo_emit_reloc(brw->batch.bo,
 361                            *surf_offset + 4,
 362                            intelObj->mt->region->bo,
 363                            surf[1] - intelObj->mt->region->bo->offset64,
 364                            I915_GEM_DOMAIN_SAMPLER, 0);
 365
 366    gen7_check_surface_setup(surf, false /* is_render_target */);
 367 }
 368
 369 /**
 370  * Create a raw surface for untyped R/W access.
 371  */
 372 static void
 373 gen7_create_raw_surface(struct brw_context *brw, drm_intel_bo *bo,
 374                         uint32_t offset, uint32_t size,
 375                         uint32_t *out_offset, bool rw)
 376 {
 377    gen7_emit_buffer_surface_state(brw,
 378                                   out_offset,
 379                                   bo,
 380                                   offset,
 381                                   BRW_SURFACEFORMAT_RAW,
 382                                   size,
 383                                   1,
 384                                   0 /* mocs */,
 385                                   true /* rw */);
 386 }
 387
 388 static void
 389 gen7_update_null_renderbuffer_surface(struct brw_context *brw, unsigned unit)
 390 {
 391    /* From the Ivy bridge PRM, Vol4 Part1 p62 (Surface Type: Programming
 392     * Notes):
 393     *
 394     *     A null surface is used in instances where an actual surface is not
 395     *     bound. When a write message is generated to a null surface, no
 396     *     actual surface is written to. When a read message (including any
 397     *     sampling engine message) is generated to a null surface, the result
 398     *     is all zeros. Note that a null surface type is allowed to be used
 399     *     with all messages, even if it is not specificially indicated as
 400     *     supported. All of the remaining fields in surface state are ignored
 401     *     for null surfaces, with the following exceptions: Width, Height,
 402     *     Depth, LOD, and Render Target View Extent fields must match the
 403     *     depth buffer’s corresponding state for all render target surfaces,
 404     *     including null.
 405     */
 406    struct gl_context *ctx = &brw->ctx;
 407
 408    /* _NEW_BUFFERS */
 409    const struct gl_framebuffer *fb = ctx->DrawBuffer;
 410    uint32_t surf_index =
 411       brw->wm.prog_data->binding_table.render_target_start + unit;
 412
 413    uint32_t *surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE, 8 * 4, 32,
 414                                     &brw->wm.base.surf_offset[surf_index]);
 415    memset(surf, 0, 8 * 4);
 416
 417    /* From the Ivybridge PRM, Volume 4, Part 1, page 65,
 418     * Tiled Surface: Programming Notes:
 419     * "If Surface Type is SURFTYPE_NULL, this field must be TRUE."
 420     */
 421    surf[0] = BRW_SURFACE_NULL << BRW_SURFACE_TYPE_SHIFT |
 422              BRW_SURFACEFORMAT_B8G8R8A8_UNORM << BRW_SURFACE_FORMAT_SHIFT |
 423              GEN7_SURFACE_TILING_Y;
 424
 425    surf[2] = SET_FIELD(fb->Width - 1, GEN7_SURFACE_WIDTH) |
 426              SET_FIELD(fb->Height - 1, GEN7_SURFACE_HEIGHT);
 427
 428    gen7_check_surface_setup(surf, true /* is_render_target */);
 429 }
 430
 431 /**
 432  * Sets up a surface state structure to point at the given region.
 433  * While it is only used for the front/back buffer currently, it should be
 434  * usable for further buffers when doing ARB_draw_buffer support.
 435  */
 436 static void
 437 gen7_update_renderbuffer_surface(struct brw_context *brw,
 438                                  struct gl_renderbuffer *rb,
 439                                  bool layered,
 440                                  unsigned int unit)
 441 {
 442    struct gl_context *ctx = &brw->ctx;
 443    struct intel_renderbuffer *irb = intel_renderbuffer(rb);
 444    struct intel_region *region = irb->mt->region;
 445    uint32_t format;
 446    /* _NEW_BUFFERS */
 447    gl_format rb_format = _mesa_get_render_format(ctx, intel_rb_format(irb));
 448    uint32_t surftype;
 449    bool is_array = false;
 450    int depth = MAX2(rb->Depth, 1);
 451    int min_array_element;
 452    const uint8_t mocs = GEN7_MOCS_L3;
 453    GLenum gl_target = rb->TexImage ?
 454                          rb->TexImage->TexObject->Target : GL_TEXTURE_2D;
 455
 456    uint32_t surf_index =
 457       brw->wm.prog_data->binding_table.render_target_start + unit;
 458
 459    uint32_t *surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE, 8 * 4, 32,
 460                                     &brw->wm.base.surf_offset[surf_index]);
 461    memset(surf, 0, 8 * 4);
 462
 463    intel_miptree_used_for_rendering(irb->mt);
 464
 465    /* Render targets can't use IMS layout */
 466    assert(irb->mt->msaa_layout != INTEL_MSAA_LAYOUT_IMS);
 467
 468    assert(brw_render_target_supported(brw, rb));
 469    format = brw->render_target_format[rb_format];
 470    if (unlikely(!brw->format_supported_as_render_target[rb_format])) {
 471       _mesa_problem(ctx, "%s: renderbuffer format %s unsupported\n",
 472                     __FUNCTION__, _mesa_get_format_name(rb_format));
 473    }
 474
 475    switch (gl_target) {
 476    case GL_TEXTURE_CUBE_MAP_ARRAY:
 477    case GL_TEXTURE_CUBE_MAP:
 478       surftype = BRW_SURFACE_2D;
 479       is_array = true;
 480       depth *= 6;
 481       break;
 482    default:
 483       surftype = translate_tex_target(gl_target);
 484       is_array = _mesa_tex_target_is_array(gl_target);
 485       break;
 486    }
 487
 488    if (layered) {
 489       min_array_element = 0;
 490    } else if (irb->mt->num_samples > 1) {
 491       min_array_element = irb->mt_layer / irb->mt->num_samples;
 492    } else {
 493       min_array_element = irb->mt_layer;
 494    }
 495
 496    surf[0] = surftype << BRW_SURFACE_TYPE_SHIFT |
 497              format << BRW_SURFACE_FORMAT_SHIFT |
 498              (irb->mt->array_spacing_lod0 ? GEN7_SURFACE_ARYSPC_LOD0
 499                                           : GEN7_SURFACE_ARYSPC_FULL) |
 500              gen7_surface_tiling_mode(region->tiling);
 501
 502    if (irb->mt->align_h == 4)
 503       surf[0] |= GEN7_SURFACE_VALIGN_4;
 504    if (irb->mt->align_w == 8)
 505       surf[0] |= GEN7_SURFACE_HALIGN_8;
 506
 507    if (is_array) {
 508       surf[0] |= GEN7_SURFACE_IS_ARRAY;
 509    }
 510
 511    surf[1] = region->bo->offset64;
 512
 513    assert(brw->has_surface_tile_offset);
 514
 515    surf[5] = SET_FIELD(mocs, GEN7_SURFACE_MOCS) |
 516              (irb->mt_level - irb->mt->first_level);
 517
 518    surf[2] = SET_FIELD(irb->mt->logical_width0 - 1, GEN7_SURFACE_WIDTH) |
 519              SET_FIELD(irb->mt->logical_height0 - 1, GEN7_SURFACE_HEIGHT);
 520
 521    surf[3] = ((depth - 1) << BRW_SURFACE_DEPTH_SHIFT) |
 522              (region->pitch - 1);
 523
 524    surf[4] = gen7_surface_msaa_bits(irb->mt->num_samples, irb->mt->msaa_layout) |
 525              min_array_element << GEN7_SURFACE_MIN_ARRAY_ELEMENT_SHIFT |
 526              (depth - 1) << GEN7_SURFACE_RENDER_TARGET_VIEW_EXTENT_SHIFT;
 527
 528    if (irb->mt->mcs_mt) {
 529       gen7_set_surface_mcs_info(brw, surf, brw->wm.base.surf_offset[surf_index],
 530                                 irb->mt->mcs_mt, true /* is RT */);
 531    }
 532
 533    surf[7] = irb->mt->fast_clear_color_value;
 534
 535    if (brw->is_haswell) {
 536       surf[7] |= (SET_FIELD(HSW_SCS_RED,   GEN7_SURFACE_SCS_R) |
 537                   SET_FIELD(HSW_SCS_GREEN, GEN7_SURFACE_SCS_G) |
 538                   SET_FIELD(HSW_SCS_BLUE,  GEN7_SURFACE_SCS_B) |
 539                   SET_FIELD(HSW_SCS_ALPHA, GEN7_SURFACE_SCS_A));
 540    }
 541
 542    drm_intel_bo_emit_reloc(brw->batch.bo,
 543                            brw->wm.base.surf_offset[surf_index] + 4,
 544                            region->bo,
 545                            surf[1] - region->bo->offset64,
 546                            I915_GEM_DOMAIN_RENDER,
 547                            I915_GEM_DOMAIN_RENDER);
 548
 549    gen7_check_surface_setup(surf, true /* is_render_target */);
 550 }
 551
 552 void
 553 gen7_init_vtable_surface_functions(struct brw_context *brw)
 554 {
 555    brw->vtbl.update_texture_surface = gen7_update_texture_surface;
 556    brw->vtbl.update_renderbuffer_surface = gen7_update_renderbuffer_surface;
 557    brw->vtbl.update_null_renderbuffer_surface =
 558       gen7_update_null_renderbuffer_surface;
 559    brw->vtbl.create_raw_surface = gen7_create_raw_surface;
 560    brw->vtbl.emit_buffer_surface_state = gen7_emit_buffer_surface_state;
 561 }