src/mesa/drivers/dri/i965/gen7_wm_surface_state.c

   1 /*
   2  * Copyright © 2011 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23 #include "main/mtypes.h"
  24 #include "main/blend.h"
  25 #include "main/samplerobj.h"
  26 #include "main/texformat.h"
  27 #include "program/prog_parameter.h"
  28
  29 #include "intel_mipmap_tree.h"
  30 #include "intel_batchbuffer.h"
  31 #include "intel_tex.h"
  32 #include "intel_fbo.h"
  33 #include "intel_buffer_objects.h"
  34
  35 #include "brw_context.h"
  36 #include "brw_state.h"
  37 #include "brw_defines.h"
  38 #include "brw_wm.h"
  39
  40 /**
  41  * Convert an swizzle enumeration (i.e. SWIZZLE_X) to one of the Gen7.5+
  42  * "Shader Channel Select" enumerations (i.e. HSW_SCS_RED)
  43  */
  44 unsigned
  45 brw_swizzle_to_scs(GLenum swizzle, bool need_green_to_blue)
  46 {
  47    switch (swizzle) {
  48    case SWIZZLE_X:
  49       return HSW_SCS_RED;
  50    case SWIZZLE_Y:
  51       return need_green_to_blue ? HSW_SCS_BLUE : HSW_SCS_GREEN;
  52    case SWIZZLE_Z:
  53       return HSW_SCS_BLUE;
  54    case SWIZZLE_W:
  55       return HSW_SCS_ALPHA;
  56    case SWIZZLE_ZERO:
  57       return HSW_SCS_ZERO;
  58    case SWIZZLE_ONE:
  59       return HSW_SCS_ONE;
  60    }
  61
  62    assert(!"Should not get here: invalid swizzle mode");
  63    return HSW_SCS_ZERO;
  64 }
  65
  66 uint32_t
  67 gen7_surface_tiling_mode(uint32_t tiling)
  68 {
  69    switch (tiling) {
  70    case I915_TILING_X:
  71       return GEN7_SURFACE_TILING_X;
  72    case I915_TILING_Y:
  73       return GEN7_SURFACE_TILING_Y;
  74    default:
  75       return GEN7_SURFACE_TILING_NONE;
  76    }
  77 }
  78
  79
  80 uint32_t
  81 gen7_surface_msaa_bits(unsigned num_samples, enum intel_msaa_layout layout)
  82 {
  83    uint32_t ss4 = 0;
  84
  85    assert(num_samples <= 8);
  86
  87    /* The SURFACE_MULTISAMPLECOUNT_X enums are simply log2(num_samples) << 3. */
  88    ss4 |= (ffs(MAX2(num_samples, 1)) - 1) << 3;
  89
  90    if (layout == INTEL_MSAA_LAYOUT_IMS)
  91       ss4 |= GEN7_SURFACE_MSFMT_DEPTH_STENCIL;
  92    else
  93       ss4 |= GEN7_SURFACE_MSFMT_MSS;
  94
  95    return ss4;
  96 }
  97
  98
  99 void
 100 gen7_set_surface_mcs_info(struct brw_context *brw,
 101                           uint32_t *surf,
 102                           uint32_t surf_offset,
 103                           const struct intel_mipmap_tree *mcs_mt,
 104                           bool is_render_target)
 105 {
 106    /* From the Ivy Bridge PRM, Vol4 Part1 p76, "MCS Base Address":
 107     *
 108     *     "The MCS surface must be stored as Tile Y."
 109     */
 110    assert(mcs_mt->tiling == I915_TILING_Y);
 111
 112    /* Compute the pitch in units of tiles.  To do this we need to divide the
 113     * pitch in bytes by 128, since a single Y-tile is 128 bytes wide.
 114     */
 115    unsigned pitch_tiles = mcs_mt->pitch / 128;
 116
 117    /* The upper 20 bits of surface state DWORD 6 are the upper 20 bits of the
 118     * GPU address of the MCS buffer; the lower 12 bits contain other control
 119     * information.  Since buffer addresses are always on 4k boundaries (and
 120     * thus have their lower 12 bits zero), we can use an ordinary reloc to do
 121     * the necessary address translation.
 122     */
 123    assert ((mcs_mt->bo->offset64 & 0xfff) == 0);
 124
 125    surf[6] = GEN7_SURFACE_MCS_ENABLE |
 126              SET_FIELD(pitch_tiles - 1, GEN7_SURFACE_MCS_PITCH) |
 127              mcs_mt->bo->offset64;
 128
 129    drm_intel_bo_emit_reloc(brw->batch.bo,
 130                            surf_offset + 6 * 4,
 131                            mcs_mt->bo,
 132                            surf[6] & 0xfff,
 133                            is_render_target ? I915_GEM_DOMAIN_RENDER
 134                            : I915_GEM_DOMAIN_SAMPLER,
 135                            is_render_target ? I915_GEM_DOMAIN_RENDER : 0);
 136 }
 137
 138
 139 void
 140 gen7_check_surface_setup(uint32_t *surf, bool is_render_target)
 141 {
 142    unsigned num_multisamples = surf[4] & INTEL_MASK(5, 3);
 143    unsigned multisampled_surface_storage_format = surf[4] & (1 << 6);
 144    unsigned surface_array_spacing = surf[0] & (1 << 10);
 145    bool is_multisampled = num_multisamples != GEN7_SURFACE_MULTISAMPLECOUNT_1;
 146
 147    (void) surface_array_spacing;
 148
 149    /* From the Ivybridge PRM, Volume 4 Part 1, page 66 (RENDER_SURFACE_STATE
 150     * dword 0 bit 10 "Surface Array Spacing" Programming Notes):
 151     *
 152     *   If Multisampled Surface Storage Format is MSFMT_MSS and Number of
 153     *   Multisamples is not MULTISAMPLECOUNT_1, this field must be set to
 154     *   ARYSPC_LOD0.
 155     */
 156    if (multisampled_surface_storage_format == GEN7_SURFACE_MSFMT_MSS
 157        && is_multisampled)
 158       assert(surface_array_spacing == GEN7_SURFACE_ARYSPC_LOD0);
 159
 160    /* From the Ivybridge PRM, Volume 4 Part 1, page 72 (RENDER_SURFACE_STATE
 161     * dword 4 bit 6 "Multisampled Surface Storage" Programming Notes):
 162     *
 163     *   All multisampled render target surfaces must have this field set to
 164     *   MSFMT_MSS.
 165     *
 166     * But also:
 167     *
 168     *   This field is ignored if Number of Multisamples is MULTISAMPLECOUNT_1.
 169     */
 170    if (is_render_target && is_multisampled) {
 171       assert(multisampled_surface_storage_format == GEN7_SURFACE_MSFMT_MSS);
 172    }
 173
 174    /* From the Ivybridge PRM, Volume 4 Part 1, page 72 (RENDER_SURFACE_STATE
 175     * dword 4 bit 6 "Multisampled Surface Storage Format" Errata):
 176     *
 177     *   If the surface’s Number of Multisamples is MULTISAMPLECOUNT_8, Width
 178     *   is >= 8192 (meaning the actual surface width is >= 8193 pixels), this
 179     *   field must be set to MSFMT_MSS.
 180     */
 181    uint32_t width = GET_FIELD(surf[2], GEN7_SURFACE_WIDTH) + 1;
 182    if (num_multisamples == GEN7_SURFACE_MULTISAMPLECOUNT_8 && width >= 8193) {
 183       assert(multisampled_surface_storage_format == GEN7_SURFACE_MSFMT_MSS);
 184    }
 185
 186    /* From the Ivybridge PRM, Volume 4 Part 1, page 72 (RENDER_SURFACE_STATE
 187     * dword 4 bit 6 "Multisampled Surface Storage Format" Errata):
 188     *
 189     *   If the surface’s Number of Multisamples is MULTISAMPLECOUNT_8,
 190     *   ((Depth+1) * (Height+1)) is > 4,194,304, OR if the surface’s Number of
 191     *   Multisamples is MULTISAMPLECOUNT_4, ((Depth+1) * (Height+1)) is >
 192     *   8,388,608, this field must be set to MSFMT_DEPTH_STENCIL.This field
 193     *   must be set to MSFMT_DEPTH_STENCIL if Surface Format is one of the
 194     *   following: I24X8_UNORM, L24X8_UNORM, A24X8_UNORM, or
 195     *   R24_UNORM_X8_TYPELESS.
 196     *
 197     * But also (from the Programming Notes):
 198     *
 199     *   This field is ignored if Number of Multisamples is MULTISAMPLECOUNT_1.
 200     */
 201    uint32_t depth = GET_FIELD(surf[3], BRW_SURFACE_DEPTH) + 1;
 202    uint32_t height = GET_FIELD(surf[2], GEN7_SURFACE_HEIGHT) + 1;
 203    if (num_multisamples == GEN7_SURFACE_MULTISAMPLECOUNT_8 &&
 204        depth * height > 4194304) {
 205       assert(multisampled_surface_storage_format ==
 206              GEN7_SURFACE_MSFMT_DEPTH_STENCIL);
 207    }
 208    if (num_multisamples == GEN7_SURFACE_MULTISAMPLECOUNT_4 &&
 209        depth * height > 8388608) {
 210       assert(multisampled_surface_storage_format ==
 211              GEN7_SURFACE_MSFMT_DEPTH_STENCIL);
 212    }
 213    if (is_multisampled) {
 214       switch (GET_FIELD(surf[0], BRW_SURFACE_FORMAT)) {
 215       case BRW_SURFACEFORMAT_I24X8_UNORM:
 216       case BRW_SURFACEFORMAT_L24X8_UNORM:
 217       case BRW_SURFACEFORMAT_A24X8_UNORM:
 218       case BRW_SURFACEFORMAT_R24_UNORM_X8_TYPELESS:
 219          assert(multisampled_surface_storage_format ==
 220                 GEN7_SURFACE_MSFMT_DEPTH_STENCIL);
 221       }
 222    }
 223 }
 224
 225 static void
 226 gen7_emit_buffer_surface_state(struct brw_context *brw,
 227                                uint32_t *out_offset,
 228                                drm_intel_bo *bo,
 229                                unsigned buffer_offset,
 230                                unsigned surface_format,
 231                                unsigned buffer_size,
 232                                unsigned pitch,
 233                                unsigned mocs,
 234                                bool rw)
 235 {
 236    uint32_t *surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE,
 237                                     8 * 4, 32, out_offset);
 238    memset(surf, 0, 8 * 4);
 239
 240    surf[0] = BRW_SURFACE_BUFFER << BRW_SURFACE_TYPE_SHIFT |
 241              surface_format << BRW_SURFACE_FORMAT_SHIFT |
 242              BRW_SURFACE_RC_READ_WRITE;
 243    surf[1] = (bo ? bo->offset64 : 0) + buffer_offset; /* reloc */
 244    surf[2] = SET_FIELD((buffer_size - 1) & 0x7f, GEN7_SURFACE_WIDTH) |
 245              SET_FIELD(((buffer_size - 1) >> 7) & 0x3fff, GEN7_SURFACE_HEIGHT);
 246    surf[3] = SET_FIELD(((buffer_size - 1) >> 21) & 0x3f, BRW_SURFACE_DEPTH) |
 247              (pitch - 1);
 248
 249    surf[5] = SET_FIELD(mocs, GEN7_SURFACE_MOCS);
 250
 251    if (brw->is_haswell) {
 252       surf[7] |= (SET_FIELD(HSW_SCS_RED,   GEN7_SURFACE_SCS_R) |
 253                   SET_FIELD(HSW_SCS_GREEN, GEN7_SURFACE_SCS_G) |
 254                   SET_FIELD(HSW_SCS_BLUE,  GEN7_SURFACE_SCS_B) |
 255                   SET_FIELD(HSW_SCS_ALPHA, GEN7_SURFACE_SCS_A));
 256    }
 257
 258    /* Emit relocation to surface contents */
 259    if (bo) {
 260       drm_intel_bo_emit_reloc(brw->batch.bo, *out_offset + 4,
 261                               bo, buffer_offset, I915_GEM_DOMAIN_SAMPLER,
 262                               (rw ? I915_GEM_DOMAIN_SAMPLER : 0));
 263    }
 264
 265    gen7_check_surface_setup(surf, false /* is_render_target */);
 266 }
 267
 268 static void
 269 gen7_update_texture_surface(struct gl_context *ctx,
 270                             unsigned unit,
 271                             uint32_t *surf_offset,
 272                             bool for_gather)
 273 {
 274    struct brw_context *brw = brw_context(ctx);
 275    struct gl_texture_object *tObj = ctx->Texture.Unit[unit]._Current;
 276    struct intel_texture_object *intelObj = intel_texture_object(tObj);
 277    struct intel_mipmap_tree *mt = intelObj->mt;
 278    struct gl_texture_image *firstImage = tObj->Image[0][tObj->BaseLevel];
 279    struct gl_sampler_object *sampler = _mesa_get_samplerobj(ctx, unit);
 280
 281    if (tObj->Target == GL_TEXTURE_BUFFER) {
 282       brw_update_buffer_texture_surface(ctx, unit, surf_offset);
 283       return;
 284    }
 285
 286    uint32_t *surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE,
 287                                     8 * 4, 32, surf_offset);
 288    memset(surf, 0, 8 * 4);
 289
 290    uint32_t tex_format = translate_tex_format(brw,
 291                                               intelObj->_Format,
 292                                               sampler->sRGBDecode);
 293
 294    if (for_gather && tex_format == BRW_SURFACEFORMAT_R32G32_FLOAT)
 295       tex_format = BRW_SURFACEFORMAT_R32G32_FLOAT_LD;
 296
 297    surf[0] = translate_tex_target(tObj->Target) << BRW_SURFACE_TYPE_SHIFT |
 298              tex_format << BRW_SURFACE_FORMAT_SHIFT |
 299              gen7_surface_tiling_mode(mt->tiling);
 300
 301    /* mask of faces present in cube map; for other surfaces MBZ. */
 302    if (tObj->Target == GL_TEXTURE_CUBE_MAP || tObj->Target == GL_TEXTURE_CUBE_MAP_ARRAY)
 303       surf[0] |= BRW_SURFACE_CUBEFACE_ENABLES;
 304
 305    if (mt->align_h == 4)
 306       surf[0] |= GEN7_SURFACE_VALIGN_4;
 307    if (mt->align_w == 8)
 308       surf[0] |= GEN7_SURFACE_HALIGN_8;
 309
 310    if (mt->logical_depth0 > 1 && tObj->Target != GL_TEXTURE_3D)
 311       surf[0] |= GEN7_SURFACE_IS_ARRAY;
 312
 313    /* if this is a view with restricted NumLayers, then
 314     * our effective depth is not just the miptree depth.
 315     */
 316    uint32_t effective_depth = (tObj->Immutable && tObj->Target != GL_TEXTURE_3D)
 317                               ? tObj->NumLayers : mt->logical_depth0;
 318
 319    if (mt->array_spacing_lod0)
 320       surf[0] |= GEN7_SURFACE_ARYSPC_LOD0;
 321
 322    surf[1] = mt->bo->offset64 + mt->offset; /* reloc */
 323
 324    surf[2] = SET_FIELD(mt->logical_width0 - 1, GEN7_SURFACE_WIDTH) |
 325              SET_FIELD(mt->logical_height0 - 1, GEN7_SURFACE_HEIGHT);
 326
 327    surf[3] = SET_FIELD(effective_depth - 1, BRW_SURFACE_DEPTH) |
 328              (mt->pitch - 1);
 329
 330    surf[4] = gen7_surface_msaa_bits(mt->num_samples, mt->msaa_layout) |
 331              SET_FIELD(tObj->MinLayer, GEN7_SURFACE_MIN_ARRAY_ELEMENT) |
 332              SET_FIELD((effective_depth - 1),
 333                        GEN7_SURFACE_RENDER_TARGET_VIEW_EXTENT);
 334
 335    surf[5] = (SET_FIELD(GEN7_MOCS_L3, GEN7_SURFACE_MOCS) |
 336               SET_FIELD(tObj->MinLevel + tObj->BaseLevel - mt->first_level, GEN7_SURFACE_MIN_LOD) |
 337               /* mip count */
 338               (intelObj->_MaxLevel - tObj->BaseLevel));
 339
 340    if (brw->is_haswell) {
 341       /* Handling GL_ALPHA as a surface format override breaks 1.30+ style
 342        * texturing functions that return a float, as our code generation always
 343        * selects the .x channel (which would always be 0).
 344        */
 345       const bool alpha_depth = tObj->DepthMode == GL_ALPHA &&
 346          (firstImage->_BaseFormat == GL_DEPTH_COMPONENT ||
 347           firstImage->_BaseFormat == GL_DEPTH_STENCIL);
 348
 349       const int swizzle = unlikely(alpha_depth)
 350          ? SWIZZLE_XYZW : brw_get_texture_swizzle(ctx, tObj);
 351
 352       const bool need_scs_green_to_blue = for_gather && tex_format == BRW_SURFACEFORMAT_R32G32_FLOAT_LD;
 353
 354       surf[7] =
 355          SET_FIELD(brw_swizzle_to_scs(GET_SWZ(swizzle, 0), need_scs_green_to_blue), GEN7_SURFACE_SCS_R) |
 356          SET_FIELD(brw_swizzle_to_scs(GET_SWZ(swizzle, 1), need_scs_green_to_blue), GEN7_SURFACE_SCS_G) |
 357          SET_FIELD(brw_swizzle_to_scs(GET_SWZ(swizzle, 2), need_scs_green_to_blue), GEN7_SURFACE_SCS_B) |
 358          SET_FIELD(brw_swizzle_to_scs(GET_SWZ(swizzle, 3), need_scs_green_to_blue), GEN7_SURFACE_SCS_A);
 359    }
 360
 361    if (mt->mcs_mt) {
 362       gen7_set_surface_mcs_info(brw, surf, *surf_offset,
 363                                 mt->mcs_mt, false /* is RT */);
 364    }
 365
 366    /* Emit relocation to surface contents */
 367    drm_intel_bo_emit_reloc(brw->batch.bo,
 368                            *surf_offset + 4,
 369                            mt->bo,
 370                            surf[1] - mt->bo->offset64,
 371                            I915_GEM_DOMAIN_SAMPLER, 0);
 372
 373    gen7_check_surface_setup(surf, false /* is_render_target */);
 374 }
 375
 376 /**
 377  * Create a raw surface for untyped R/W access.
 378  */
 379 static void
 380 gen7_create_raw_surface(struct brw_context *brw, drm_intel_bo *bo,
 381                         uint32_t offset, uint32_t size,
 382                         uint32_t *out_offset, bool rw)
 383 {
 384    gen7_emit_buffer_surface_state(brw,
 385                                   out_offset,
 386                                   bo,
 387                                   offset,
 388                                   BRW_SURFACEFORMAT_RAW,
 389                                   size,
 390                                   1,
 391                                   0 /* mocs */,
 392                                   true /* rw */);
 393 }
 394
 395 static void
 396 gen7_update_null_renderbuffer_surface(struct brw_context *brw, unsigned unit)
 397 {
 398    /* From the Ivy bridge PRM, Vol4 Part1 p62 (Surface Type: Programming
 399     * Notes):
 400     *
 401     *     A null surface is used in instances where an actual surface is not
 402     *     bound. When a write message is generated to a null surface, no
 403     *     actual surface is written to. When a read message (including any
 404     *     sampling engine message) is generated to a null surface, the result
 405     *     is all zeros. Note that a null surface type is allowed to be used
 406     *     with all messages, even if it is not specificially indicated as
 407     *     supported. All of the remaining fields in surface state are ignored
 408     *     for null surfaces, with the following exceptions: Width, Height,
 409     *     Depth, LOD, and Render Target View Extent fields must match the
 410     *     depth buffer’s corresponding state for all render target surfaces,
 411     *     including null.
 412     */
 413    struct gl_context *ctx = &brw->ctx;
 414
 415    /* _NEW_BUFFERS */
 416    const struct gl_framebuffer *fb = ctx->DrawBuffer;
 417    uint32_t surf_index =
 418       brw->wm.prog_data->binding_table.render_target_start + unit;
 419
 420    uint32_t *surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE, 8 * 4, 32,
 421                                     &brw->wm.base.surf_offset[surf_index]);
 422    memset(surf, 0, 8 * 4);
 423
 424    /* From the Ivybridge PRM, Volume 4, Part 1, page 65,
 425     * Tiled Surface: Programming Notes:
 426     * "If Surface Type is SURFTYPE_NULL, this field must be TRUE."
 427     */
 428    surf[0] = BRW_SURFACE_NULL << BRW_SURFACE_TYPE_SHIFT |
 429              BRW_SURFACEFORMAT_B8G8R8A8_UNORM << BRW_SURFACE_FORMAT_SHIFT |
 430              GEN7_SURFACE_TILING_Y;
 431
 432    surf[2] = SET_FIELD(fb->Width - 1, GEN7_SURFACE_WIDTH) |
 433              SET_FIELD(fb->Height - 1, GEN7_SURFACE_HEIGHT);
 434
 435    gen7_check_surface_setup(surf, true /* is_render_target */);
 436 }
 437
 438 /**
 439  * Sets up a surface state structure to point at the given region.
 440  * While it is only used for the front/back buffer currently, it should be
 441  * usable for further buffers when doing ARB_draw_buffer support.
 442  */
 443 static void
 444 gen7_update_renderbuffer_surface(struct brw_context *brw,
 445                                  struct gl_renderbuffer *rb,
 446                                  bool layered,
 447                                  unsigned int unit)
 448 {
 449    struct gl_context *ctx = &brw->ctx;
 450    struct intel_renderbuffer *irb = intel_renderbuffer(rb);
 451    struct intel_mipmap_tree *mt = irb->mt;
 452    uint32_t format;
 453    /* _NEW_BUFFERS */
 454    mesa_format rb_format = _mesa_get_render_format(ctx, intel_rb_format(irb));
 455    uint32_t surftype;
 456    bool is_array = false;
 457    int depth = MAX2(irb->layer_count, 1);
 458    const uint8_t mocs = GEN7_MOCS_L3;
 459
 460    int min_array_element = irb->mt_layer / MAX2(mt->num_samples, 1);
 461
 462    GLenum gl_target = rb->TexImage ?
 463                          rb->TexImage->TexObject->Target : GL_TEXTURE_2D;
 464
 465    uint32_t surf_index =
 466       brw->wm.prog_data->binding_table.render_target_start + unit;
 467
 468    uint32_t *surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE, 8 * 4, 32,
 469                                     &brw->wm.base.surf_offset[surf_index]);
 470    memset(surf, 0, 8 * 4);
 471
 472    intel_miptree_used_for_rendering(irb->mt);
 473
 474    /* Render targets can't use IMS layout */
 475    assert(irb->mt->msaa_layout != INTEL_MSAA_LAYOUT_IMS);
 476
 477    assert(brw_render_target_supported(brw, rb));
 478    format = brw->render_target_format[rb_format];
 479    if (unlikely(!brw->format_supported_as_render_target[rb_format])) {
 480       _mesa_problem(ctx, "%s: renderbuffer format %s unsupported\n",
 481                     __FUNCTION__, _mesa_get_format_name(rb_format));
 482    }
 483
 484    switch (gl_target) {
 485    case GL_TEXTURE_CUBE_MAP_ARRAY:
 486    case GL_TEXTURE_CUBE_MAP:
 487       surftype = BRW_SURFACE_2D;
 488       is_array = true;
 489       depth *= 6;
 490       break;
 491    case GL_TEXTURE_3D:
 492       depth = MAX2(rb->Depth, 1);
 493       /* fallthrough */
 494    default:
 495       surftype = translate_tex_target(gl_target);
 496       is_array = _mesa_tex_target_is_array(gl_target);
 497       break;
 498    }
 499
 500    surf[0] = surftype << BRW_SURFACE_TYPE_SHIFT |
 501              format << BRW_SURFACE_FORMAT_SHIFT |
 502              (irb->mt->array_spacing_lod0 ? GEN7_SURFACE_ARYSPC_LOD0
 503                                           : GEN7_SURFACE_ARYSPC_FULL) |
 504              gen7_surface_tiling_mode(mt->tiling);
 505
 506    if (irb->mt->align_h == 4)
 507       surf[0] |= GEN7_SURFACE_VALIGN_4;
 508    if (irb->mt->align_w == 8)
 509       surf[0] |= GEN7_SURFACE_HALIGN_8;
 510
 511    if (is_array) {
 512       surf[0] |= GEN7_SURFACE_IS_ARRAY;
 513    }
 514
 515    surf[1] = mt->bo->offset64;
 516
 517    assert(brw->has_surface_tile_offset);
 518
 519    surf[5] = SET_FIELD(mocs, GEN7_SURFACE_MOCS) |
 520              (irb->mt_level - irb->mt->first_level);
 521
 522    surf[2] = SET_FIELD(irb->mt->logical_width0 - 1, GEN7_SURFACE_WIDTH) |
 523              SET_FIELD(irb->mt->logical_height0 - 1, GEN7_SURFACE_HEIGHT);
 524
 525    surf[3] = ((depth - 1) << BRW_SURFACE_DEPTH_SHIFT) |
 526              (mt->pitch - 1);
 527
 528    surf[4] = gen7_surface_msaa_bits(irb->mt->num_samples, irb->mt->msaa_layout) |
 529              min_array_element << GEN7_SURFACE_MIN_ARRAY_ELEMENT_SHIFT |
 530              (depth - 1) << GEN7_SURFACE_RENDER_TARGET_VIEW_EXTENT_SHIFT;
 531
 532    if (irb->mt->mcs_mt) {
 533       gen7_set_surface_mcs_info(brw, surf, brw->wm.base.surf_offset[surf_index],
 534                                 irb->mt->mcs_mt, true /* is RT */);
 535    }
 536
 537    surf[7] = irb->mt->fast_clear_color_value;
 538
 539    if (brw->is_haswell) {
 540       surf[7] |= (SET_FIELD(HSW_SCS_RED,   GEN7_SURFACE_SCS_R) |
 541                   SET_FIELD(HSW_SCS_GREEN, GEN7_SURFACE_SCS_G) |
 542                   SET_FIELD(HSW_SCS_BLUE,  GEN7_SURFACE_SCS_B) |
 543                   SET_FIELD(HSW_SCS_ALPHA, GEN7_SURFACE_SCS_A));
 544    }
 545
 546    drm_intel_bo_emit_reloc(brw->batch.bo,
 547                            brw->wm.base.surf_offset[surf_index] + 4,
 548                            mt->bo,
 549                            surf[1] - mt->bo->offset64,
 550                            I915_GEM_DOMAIN_RENDER,
 551                            I915_GEM_DOMAIN_RENDER);
 552
 553    gen7_check_surface_setup(surf, true /* is_render_target */);
 554 }
 555
 556 void
 557 gen7_init_vtable_surface_functions(struct brw_context *brw)
 558 {
 559    brw->vtbl.update_texture_surface = gen7_update_texture_surface;
 560    brw->vtbl.update_renderbuffer_surface = gen7_update_renderbuffer_surface;
 561    brw->vtbl.update_null_renderbuffer_surface =
 562       gen7_update_null_renderbuffer_surface;
 563    brw->vtbl.create_raw_surface = gen7_create_raw_surface;
 564    brw->vtbl.emit_buffer_surface_state = gen7_emit_buffer_surface_state;
 565 }