src/mesa/drivers/dri/i965/gen7_wm_surface_state.c

   1 /*
   2  * Copyright © 2011 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23 #include "main/mtypes.h"
  24 #include "main/samplerobj.h"
  25 #include "program/prog_parameter.h"
  26
  27 #include "intel_mipmap_tree.h"
  28 #include "intel_batchbuffer.h"
  29 #include "intel_tex.h"
  30 #include "intel_fbo.h"
  31
  32 #include "brw_context.h"
  33 #include "brw_state.h"
  34 #include "brw_defines.h"
  35 #include "brw_wm.h"
  36
  37 static void
  38 gen7_set_surface_tiling(struct gen7_surface_state *surf, uint32_t tiling)
  39 {
  40    switch (tiling) {
  41    case I915_TILING_NONE:
  42       surf->ss0.tiled_surface = 0;
  43       surf->ss0.tile_walk = 0;
  44       break;
  45    case I915_TILING_X:
  46       surf->ss0.tiled_surface = 1;
  47       surf->ss0.tile_walk = BRW_TILEWALK_XMAJOR;
  48       break;
  49    case I915_TILING_Y:
  50       surf->ss0.tiled_surface = 1;
  51       surf->ss0.tile_walk = BRW_TILEWALK_YMAJOR;
  52       break;
  53    }
  54 }
  55
  56 static void
  57 gen7_update_texture_surface(struct gl_context *ctx, GLuint unit)
  58 {
  59    struct brw_context *brw = brw_context(ctx);
  60    struct gl_texture_object *tObj = ctx->Texture.Unit[unit]._Current;
  61    struct intel_texture_object *intelObj = intel_texture_object(tObj);
  62    struct intel_mipmap_tree *mt = intelObj->mt;
  63    struct gl_texture_image *firstImage = tObj->Image[0][tObj->BaseLevel];
  64    struct gl_sampler_object *sampler = _mesa_get_samplerobj(ctx, unit);
  65    const GLuint surf_index = SURF_INDEX_TEXTURE(unit);
  66    struct gen7_surface_state *surf;
  67    int width, height, depth;
  68
  69    intel_miptree_get_dimensions_for_image(firstImage, &width, &height, &depth);
  70
  71    surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE,
  72                           sizeof(*surf), 32, &brw->bind.surf_offset[surf_index]);
  73    memset(surf, 0, sizeof(*surf));
  74
  75    if (mt->align_h == 4)
  76       surf->ss0.vertical_alignment = 1;
  77    if (mt->align_w == 8)
  78       surf->ss0.horizontal_alignment = 1;
  79
  80    surf->ss0.surface_type = translate_tex_target(tObj->Target);
  81    surf->ss0.surface_format = translate_tex_format(mt->format,
  82                                                    firstImage->InternalFormat,
  83                                                    sampler->DepthMode,
  84                                                    sampler->sRGBDecode);
  85    if (tObj->Target == GL_TEXTURE_CUBE_MAP) {
  86       surf->ss0.cube_pos_x = 1;
  87       surf->ss0.cube_pos_y = 1;
  88       surf->ss0.cube_pos_z = 1;
  89       surf->ss0.cube_neg_x = 1;
  90       surf->ss0.cube_neg_y = 1;
  91       surf->ss0.cube_neg_z = 1;
  92    }
  93
  94    surf->ss0.is_array = depth > 1 && tObj->Target != GL_TEXTURE_3D;
  95
  96    gen7_set_surface_tiling(surf, intelObj->mt->region->tiling);
  97
  98    /* ss0 remaining fields:
  99     * - vert_line_stride (exists on gen6 but we ignore it)
 100     * - vert_line_stride_ofs (exists on gen6 but we ignore it)
 101     * - surface_array_spacing
 102     * - render_cache_read_write (exists on gen6 but ignored here)
 103     */
 104
 105    surf->ss1.base_addr = intelObj->mt->region->bo->offset; /* reloc */
 106
 107    surf->ss2.width = width - 1;
 108    surf->ss2.height = height - 1;
 109
 110    surf->ss3.pitch = (intelObj->mt->region->pitch * intelObj->mt->cpp) - 1;
 111    surf->ss3.depth = depth - 1;
 112
 113    /* ss4: ignored? */
 114
 115    surf->ss5.mip_count = intelObj->_MaxLevel - tObj->BaseLevel;
 116    surf->ss5.min_lod = 0;
 117
 118    /* ss5 remaining fields:
 119     * - x_offset (N/A for textures?)
 120     * - y_offset (ditto)
 121     * - cache_control
 122     */
 123
 124    /* Emit relocation to surface contents */
 125    drm_intel_bo_emit_reloc(brw->intel.batch.bo,
 126                            brw->bind.surf_offset[surf_index] +
 127                            offsetof(struct gen7_surface_state, ss1),
 128                            intelObj->mt->region->bo, 0,
 129                            I915_GEM_DOMAIN_SAMPLER, 0);
 130 }
 131
 132 /**
 133  * Create the constant buffer surface.  Vertex/fragment shader constants will
 134  * be read from this buffer with Data Port Read instructions/messages.
 135  */
 136 void
 137 gen7_create_constant_surface(struct brw_context *brw,
 138                              drm_intel_bo *bo,
 139                              int width,
 140                              uint32_t *out_offset)
 141 {
 142    const GLint w = width - 1;
 143    struct gen7_surface_state *surf;
 144
 145    surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE,
 146                           sizeof(*surf), 32, out_offset);
 147    memset(surf, 0, sizeof(*surf));
 148
 149    surf->ss0.surface_type = BRW_SURFACE_BUFFER;
 150    surf->ss0.surface_format = BRW_SURFACEFORMAT_R32G32B32A32_FLOAT;
 151
 152    surf->ss0.render_cache_read_write = 1;
 153
 154    assert(bo);
 155    surf->ss1.base_addr = bo->offset; /* reloc */
 156
 157    surf->ss2.width = w & 0x7f;            /* bits 6:0 of size or width */
 158    surf->ss2.height = (w >> 7) & 0x1fff;  /* bits 19:7 of size or width */
 159    surf->ss3.depth = (w >> 20) & 0x7f;    /* bits 26:20 of size or width */
 160    surf->ss3.pitch = (16 - 1); /* ignored */
 161    gen7_set_surface_tiling(surf, I915_TILING_NONE); /* tiling now allowed */
 162
 163    /* Emit relocation to surface contents.  Section 5.1.1 of the gen4
 164     * bspec ("Data Cache") says that the data cache does not exist as
 165     * a separate cache and is just the sampler cache.
 166     */
 167    drm_intel_bo_emit_reloc(brw->intel.batch.bo,
 168                            (*out_offset +
 169                             offsetof(struct gen7_surface_state, ss1)),
 170                            bo, 0,
 171                            I915_GEM_DOMAIN_SAMPLER, 0);
 172 }
 173
 174 static void
 175 gen7_update_null_renderbuffer_surface(struct brw_context *brw, unsigned unit)
 176 {
 177    struct gen7_surface_state *surf;
 178
 179    surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE,
 180                           sizeof(*surf), 32, &brw->bind.surf_offset[unit]);
 181    memset(surf, 0, sizeof(*surf));
 182
 183    surf->ss0.surface_type = BRW_SURFACE_NULL;
 184    surf->ss0.surface_format = BRW_SURFACEFORMAT_B8G8R8A8_UNORM;
 185 }
 186
 187 /**
 188  * Sets up a surface state structure to point at the given region.
 189  * While it is only used for the front/back buffer currently, it should be
 190  * usable for further buffers when doing ARB_draw_buffer support.
 191  */
 192 static void
 193 gen7_update_renderbuffer_surface(struct brw_context *brw,
 194                                  struct gl_renderbuffer *rb,
 195                                  unsigned int unit)
 196 {
 197    struct intel_context *intel = &brw->intel;
 198    struct gl_context *ctx = &intel->ctx;
 199    struct intel_renderbuffer *irb = intel_renderbuffer(rb);
 200    struct intel_region *region = irb->mt->region;
 201    struct gen7_surface_state *surf;
 202    uint32_t tile_x, tile_y;
 203    gl_format rb_format = intel_rb_format(irb);
 204
 205    surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE,
 206                           sizeof(*surf), 32, &brw->bind.surf_offset[unit]);
 207    memset(surf, 0, sizeof(*surf));
 208
 209    if (irb->mt->align_h == 4)
 210       surf->ss0.vertical_alignment = 1;
 211    if (irb->mt->align_w == 8)
 212       surf->ss0.horizontal_alignment = 1;
 213
 214    switch (rb_format) {
 215    case MESA_FORMAT_SARGB8:
 216       /* without GL_EXT_framebuffer_sRGB we shouldn't bind sRGB
 217          surfaces to the blend/update as sRGB */
 218       if (ctx->Color.sRGBEnabled)
 219          surf->ss0.surface_format = brw_format_for_mesa_format(rb_format);
 220       else
 221          surf->ss0.surface_format = BRW_SURFACEFORMAT_B8G8R8A8_UNORM;
 222       break;
 223    default:
 224       assert(brw_render_target_supported(intel, rb));
 225       surf->ss0.surface_format = brw->render_target_format[rb_format];
 226       if (unlikely(!brw->format_supported_as_render_target[rb_format])) {
 227          _mesa_problem(ctx, "%s: renderbuffer format %s unsupported\n",
 228                        __FUNCTION__, _mesa_get_format_name(rb_format));
 229       }
 230        break;
 231    }
 232
 233    surf->ss0.surface_type = BRW_SURFACE_2D;
 234    /* reloc */
 235    surf->ss1.base_addr = intel_renderbuffer_tile_offsets(irb, &tile_x, &tile_y);
 236    surf->ss1.base_addr += region->bo->offset; /* reloc */
 237
 238    assert(brw->has_surface_tile_offset);
 239    /* Note that the low bits of these fields are missing, so
 240     * there's the possibility of getting in trouble.
 241     */
 242    assert(tile_x % 4 == 0);
 243    assert(tile_y % 2 == 0);
 244    surf->ss5.x_offset = tile_x / 4;
 245    surf->ss5.y_offset = tile_y / 2;
 246
 247    surf->ss2.width = rb->Width - 1;
 248    surf->ss2.height = rb->Height - 1;
 249    gen7_set_surface_tiling(surf, region->tiling);
 250    surf->ss3.pitch = (region->pitch * region->cpp) - 1;
 251
 252    drm_intel_bo_emit_reloc(brw->intel.batch.bo,
 253                            brw->bind.surf_offset[unit] +
 254                            offsetof(struct gen7_surface_state, ss1),
 255                            region->bo,
 256                            surf->ss1.base_addr - region->bo->offset,
 257                            I915_GEM_DOMAIN_RENDER,
 258                            I915_GEM_DOMAIN_RENDER);
 259 }
 260
 261 void
 262 gen7_init_vtable_surface_functions(struct brw_context *brw)
 263 {
 264    struct intel_context *intel = &brw->intel;
 265
 266    intel->vtbl.update_texture_surface = gen7_update_texture_surface;
 267    intel->vtbl.update_renderbuffer_surface = gen7_update_renderbuffer_surface;
 268    intel->vtbl.update_null_renderbuffer_surface =
 269       gen7_update_null_renderbuffer_surface;
 270    intel->vtbl.create_constant_surface = gen7_create_constant_surface;
 271 }