src/mesa/drivers/dri/i965/gen7_wm_surface_state.c

   1 /*
   2  * Copyright © 2011 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23 #include "main/mtypes.h"
  24 #include "main/blend.h"
  25 #include "main/samplerobj.h"
  26 #include "main/texformat.h"
  27 #include "main/teximage.h"
  28 #include "program/prog_parameter.h"
  29 #include "program/prog_instruction.h"
  30
  31 #include "intel_mipmap_tree.h"
  32 #include "intel_batchbuffer.h"
  33 #include "intel_tex.h"
  34 #include "intel_fbo.h"
  35 #include "intel_buffer_objects.h"
  36
  37 #include "brw_context.h"
  38 #include "brw_state.h"
  39 #include "brw_defines.h"
  40 #include "brw_wm.h"
  41
  42 uint32_t
  43 gen7_surface_tiling_mode(uint32_t tiling)
  44 {
  45    switch (tiling) {
  46    case I915_TILING_X:
  47       return GEN7_SURFACE_TILING_X;
  48    case I915_TILING_Y:
  49       return GEN7_SURFACE_TILING_Y;
  50    default:
  51       return GEN7_SURFACE_TILING_NONE;
  52    }
  53 }
  54
  55
  56 uint32_t
  57 gen7_surface_msaa_bits(unsigned num_samples, enum intel_msaa_layout layout)
  58 {
  59    uint32_t ss4 = 0;
  60
  61    assert(num_samples <= 16);
  62
  63    /* The SURFACE_MULTISAMPLECOUNT_X enums are simply log2(num_samples) << 3. */
  64    ss4 |= (ffs(MAX2(num_samples, 1)) - 1) << 3;
  65
  66    if (layout == INTEL_MSAA_LAYOUT_IMS)
  67       ss4 |= GEN7_SURFACE_MSFMT_DEPTH_STENCIL;
  68    else
  69       ss4 |= GEN7_SURFACE_MSFMT_MSS;
  70
  71    return ss4;
  72 }
  73
  74
  75 void
  76 gen7_set_surface_mcs_info(struct brw_context *brw,
  77                           uint32_t *surf,
  78                           uint32_t surf_offset,
  79                           const struct intel_mipmap_tree *mcs_mt,
  80                           bool is_render_target)
  81 {
  82    /* From the Ivy Bridge PRM, Vol4 Part1 p76, "MCS Base Address":
  83     *
  84     *     "The MCS surface must be stored as Tile Y."
  85     */
  86    assert(mcs_mt->tiling == I915_TILING_Y);
  87
  88    /* Compute the pitch in units of tiles.  To do this we need to divide the
  89     * pitch in bytes by 128, since a single Y-tile is 128 bytes wide.
  90     */
  91    unsigned pitch_tiles = mcs_mt->pitch / 128;
  92
  93    /* The upper 20 bits of surface state DWORD 6 are the upper 20 bits of the
  94     * GPU address of the MCS buffer; the lower 12 bits contain other control
  95     * information.  Since buffer addresses are always on 4k boundaries (and
  96     * thus have their lower 12 bits zero), we can use an ordinary reloc to do
  97     * the necessary address translation.
  98     */
  99    assert ((mcs_mt->bo->offset64 & 0xfff) == 0);
 100
 101    surf[6] = GEN7_SURFACE_MCS_ENABLE |
 102              SET_FIELD(pitch_tiles - 1, GEN7_SURFACE_MCS_PITCH) |
 103              mcs_mt->bo->offset64;
 104
 105    drm_intel_bo_emit_reloc(brw->batch.bo,
 106                            surf_offset + 6 * 4,
 107                            mcs_mt->bo,
 108                            surf[6] & 0xfff,
 109                            is_render_target ? I915_GEM_DOMAIN_RENDER
 110                            : I915_GEM_DOMAIN_SAMPLER,
 111                            is_render_target ? I915_GEM_DOMAIN_RENDER : 0);
 112 }
 113
 114
 115 void
 116 gen7_check_surface_setup(uint32_t *surf, bool is_render_target)
 117 {
 118    unsigned num_multisamples = surf[4] & INTEL_MASK(5, 3);
 119    unsigned multisampled_surface_storage_format = surf[4] & (1 << 6);
 120    unsigned surface_array_spacing = surf[0] & (1 << 10);
 121    bool is_multisampled = num_multisamples != GEN7_SURFACE_MULTISAMPLECOUNT_1;
 122
 123    (void) surface_array_spacing;
 124
 125    /* From the Ivybridge PRM, Volume 4 Part 1, page 66 (RENDER_SURFACE_STATE
 126     * dword 0 bit 10 "Surface Array Spacing" Programming Notes):
 127     *
 128     *   If Multisampled Surface Storage Format is MSFMT_MSS and Number of
 129     *   Multisamples is not MULTISAMPLECOUNT_1, this field must be set to
 130     *   ARYSPC_LOD0.
 131     */
 132    if (multisampled_surface_storage_format == GEN7_SURFACE_MSFMT_MSS
 133        && is_multisampled)
 134       assert(surface_array_spacing == GEN7_SURFACE_ARYSPC_LOD0);
 135
 136    /* From the Ivybridge PRM, Volume 4 Part 1, page 72 (RENDER_SURFACE_STATE
 137     * dword 4 bit 6 "Multisampled Surface Storage" Programming Notes):
 138     *
 139     *   All multisampled render target surfaces must have this field set to
 140     *   MSFMT_MSS.
 141     *
 142     * But also:
 143     *
 144     *   This field is ignored if Number of Multisamples is MULTISAMPLECOUNT_1.
 145     */
 146    if (is_render_target && is_multisampled) {
 147       assert(multisampled_surface_storage_format == GEN7_SURFACE_MSFMT_MSS);
 148    }
 149
 150    /* From the Ivybridge PRM, Volume 4 Part 1, page 72 (RENDER_SURFACE_STATE
 151     * dword 4 bit 6 "Multisampled Surface Storage Format" Errata):
 152     *
 153     *   If the surface’s Number of Multisamples is MULTISAMPLECOUNT_8, Width
 154     *   is >= 8192 (meaning the actual surface width is >= 8193 pixels), this
 155     *   field must be set to MSFMT_MSS.
 156     */
 157    uint32_t width = GET_FIELD(surf[2], GEN7_SURFACE_WIDTH) + 1;
 158    if (num_multisamples == GEN7_SURFACE_MULTISAMPLECOUNT_8 && width >= 8193) {
 159       assert(multisampled_surface_storage_format == GEN7_SURFACE_MSFMT_MSS);
 160    }
 161
 162    /* From the Ivybridge PRM, Volume 4 Part 1, page 72 (RENDER_SURFACE_STATE
 163     * dword 4 bit 6 "Multisampled Surface Storage Format" Errata):
 164     *
 165     *   If the surface’s Number of Multisamples is MULTISAMPLECOUNT_8,
 166     *   ((Depth+1) * (Height+1)) is > 4,194,304, OR if the surface’s Number of
 167     *   Multisamples is MULTISAMPLECOUNT_4, ((Depth+1) * (Height+1)) is >
 168     *   8,388,608, this field must be set to MSFMT_DEPTH_STENCIL.This field
 169     *   must be set to MSFMT_DEPTH_STENCIL if Surface Format is one of the
 170     *   following: I24X8_UNORM, L24X8_UNORM, A24X8_UNORM, or
 171     *   R24_UNORM_X8_TYPELESS.
 172     *
 173     * But also (from the Programming Notes):
 174     *
 175     *   This field is ignored if Number of Multisamples is MULTISAMPLECOUNT_1.
 176     */
 177    uint32_t depth = GET_FIELD(surf[3], BRW_SURFACE_DEPTH) + 1;
 178    uint32_t height = GET_FIELD(surf[2], GEN7_SURFACE_HEIGHT) + 1;
 179    if (num_multisamples == GEN7_SURFACE_MULTISAMPLECOUNT_8 &&
 180        depth * height > 4194304) {
 181       assert(multisampled_surface_storage_format ==
 182              GEN7_SURFACE_MSFMT_DEPTH_STENCIL);
 183    }
 184    if (num_multisamples == GEN7_SURFACE_MULTISAMPLECOUNT_4 &&
 185        depth * height > 8388608) {
 186       assert(multisampled_surface_storage_format ==
 187              GEN7_SURFACE_MSFMT_DEPTH_STENCIL);
 188    }
 189    if (is_multisampled) {
 190       switch (GET_FIELD(surf[0], BRW_SURFACE_FORMAT)) {
 191       case BRW_SURFACEFORMAT_I24X8_UNORM:
 192       case BRW_SURFACEFORMAT_L24X8_UNORM:
 193       case BRW_SURFACEFORMAT_A24X8_UNORM:
 194       case BRW_SURFACEFORMAT_R24_UNORM_X8_TYPELESS:
 195          assert(multisampled_surface_storage_format ==
 196                 GEN7_SURFACE_MSFMT_DEPTH_STENCIL);
 197       }
 198    }
 199 }
 200
 201 static void
 202 gen7_emit_buffer_surface_state(struct brw_context *brw,
 203                                uint32_t *out_offset,
 204                                drm_intel_bo *bo,
 205                                unsigned buffer_offset,
 206                                unsigned surface_format,
 207                                unsigned buffer_size,
 208                                unsigned pitch,
 209                                bool rw)
 210 {
 211    uint32_t *surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE,
 212                                     8 * 4, 32, out_offset);
 213    memset(surf, 0, 8 * 4);
 214
 215    surf[0] = BRW_SURFACE_BUFFER << BRW_SURFACE_TYPE_SHIFT |
 216              surface_format << BRW_SURFACE_FORMAT_SHIFT |
 217              BRW_SURFACE_RC_READ_WRITE;
 218    surf[1] = (bo ? bo->offset64 : 0) + buffer_offset; /* reloc */
 219    surf[2] = SET_FIELD((buffer_size - 1) & 0x7f, GEN7_SURFACE_WIDTH) |
 220              SET_FIELD(((buffer_size - 1) >> 7) & 0x3fff, GEN7_SURFACE_HEIGHT);
 221    if (surface_format == BRW_SURFACEFORMAT_RAW)
 222       surf[3] = SET_FIELD(((buffer_size - 1) >> 21) & 0x3ff, BRW_SURFACE_DEPTH);
 223    else
 224       surf[3] = SET_FIELD(((buffer_size - 1) >> 21) & 0x3f, BRW_SURFACE_DEPTH);
 225    surf[3] |= (pitch - 1);
 226
 227    surf[5] = SET_FIELD(GEN7_MOCS_L3, GEN7_SURFACE_MOCS);
 228
 229    if (brw->is_haswell) {
 230       surf[7] |= (SET_FIELD(HSW_SCS_RED,   GEN7_SURFACE_SCS_R) |
 231                   SET_FIELD(HSW_SCS_GREEN, GEN7_SURFACE_SCS_G) |
 232                   SET_FIELD(HSW_SCS_BLUE,  GEN7_SURFACE_SCS_B) |
 233                   SET_FIELD(HSW_SCS_ALPHA, GEN7_SURFACE_SCS_A));
 234    }
 235
 236    /* Emit relocation to surface contents */
 237    if (bo) {
 238       drm_intel_bo_emit_reloc(brw->batch.bo, *out_offset + 4,
 239                               bo, buffer_offset, I915_GEM_DOMAIN_SAMPLER,
 240                               (rw ? I915_GEM_DOMAIN_SAMPLER : 0));
 241    }
 242
 243    gen7_check_surface_setup(surf, false /* is_render_target */);
 244 }
 245
 246 /**
 247  * Creates a null surface.
 248  *
 249  * This is used when the shader doesn't write to any color output.  An FB
 250  * write to target 0 will still be emitted, because that's how the thread is
 251  * terminated (and computed depth is returned), so we need to have the
 252  * hardware discard the target 0 color output..
 253  */
 254 static void
 255 gen7_emit_null_surface_state(struct brw_context *brw,
 256                              unsigned width,
 257                              unsigned height,
 258                              unsigned samples,
 259                              uint32_t *out_offset)
 260 {
 261    /* From the Ivy bridge PRM, Vol4 Part1 p62 (Surface Type: Programming
 262     * Notes):
 263     *
 264     *     A null surface is used in instances where an actual surface is not
 265     *     bound. When a write message is generated to a null surface, no
 266     *     actual surface is written to. When a read message (including any
 267     *     sampling engine message) is generated to a null surface, the result
 268     *     is all zeros. Note that a null surface type is allowed to be used
 269     *     with all messages, even if it is not specificially indicated as
 270     *     supported. All of the remaining fields in surface state are ignored
 271     *     for null surfaces, with the following exceptions: Width, Height,
 272     *     Depth, LOD, and Render Target View Extent fields must match the
 273     *     depth buffer’s corresponding state for all render target surfaces,
 274     *     including null.
 275     */
 276    uint32_t *surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE, 8 * 4, 32,
 277                                     out_offset);
 278    memset(surf, 0, 8 * 4);
 279
 280    /* From the Ivybridge PRM, Volume 4, Part 1, page 65,
 281     * Tiled Surface: Programming Notes:
 282     * "If Surface Type is SURFTYPE_NULL, this field must be TRUE."
 283     */
 284    surf[0] = BRW_SURFACE_NULL << BRW_SURFACE_TYPE_SHIFT |
 285              BRW_SURFACEFORMAT_B8G8R8A8_UNORM << BRW_SURFACE_FORMAT_SHIFT |
 286              GEN7_SURFACE_TILING_Y;
 287
 288    surf[2] = SET_FIELD(width - 1, GEN7_SURFACE_WIDTH) |
 289              SET_FIELD(height - 1, GEN7_SURFACE_HEIGHT);
 290
 291    gen7_check_surface_setup(surf, true /* is_render_target */);
 292 }
 293
 294 /**
 295  * Sets up a surface state structure to point at the given region.
 296  * While it is only used for the front/back buffer currently, it should be
 297  * usable for further buffers when doing ARB_draw_buffer support.
 298  */
 299 static uint32_t
 300 gen7_update_renderbuffer_surface(struct brw_context *brw,
 301                                  struct gl_renderbuffer *rb,
 302                                  bool layered, unsigned unit /* unused */,
 303                                  uint32_t surf_index)
 304 {
 305    struct gl_context *ctx = &brw->ctx;
 306    struct intel_renderbuffer *irb = intel_renderbuffer(rb);
 307    struct intel_mipmap_tree *mt = irb->mt;
 308    uint32_t format;
 309    /* _NEW_BUFFERS */
 310    mesa_format rb_format = _mesa_get_render_format(ctx, intel_rb_format(irb));
 311    uint32_t surftype;
 312    bool is_array = false;
 313    int depth = MAX2(irb->layer_count, 1);
 314    const uint8_t mocs = GEN7_MOCS_L3;
 315    uint32_t offset;
 316
 317    int min_array_element = irb->mt_layer / MAX2(mt->num_samples, 1);
 318
 319    GLenum gl_target = rb->TexImage ?
 320                          rb->TexImage->TexObject->Target : GL_TEXTURE_2D;
 321
 322    uint32_t *surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE, 8 * 4, 32,
 323                                     &offset);
 324    memset(surf, 0, 8 * 4);
 325
 326    intel_miptree_used_for_rendering(irb->mt);
 327
 328    /* Render targets can't use IMS layout */
 329    assert(irb->mt->msaa_layout != INTEL_MSAA_LAYOUT_IMS);
 330
 331    assert(brw_render_target_supported(brw, rb));
 332    format = brw->render_target_format[rb_format];
 333    if (unlikely(!brw->format_supported_as_render_target[rb_format])) {
 334       _mesa_problem(ctx, "%s: renderbuffer format %s unsupported\n",
 335                     __func__, _mesa_get_format_name(rb_format));
 336    }
 337
 338    switch (gl_target) {
 339    case GL_TEXTURE_CUBE_MAP_ARRAY:
 340    case GL_TEXTURE_CUBE_MAP:
 341       surftype = BRW_SURFACE_2D;
 342       is_array = true;
 343       depth *= 6;
 344       break;
 345    case GL_TEXTURE_3D:
 346       depth = MAX2(irb->mt->logical_depth0, 1);
 347       /* fallthrough */
 348    default:
 349       surftype = translate_tex_target(gl_target);
 350       is_array = _mesa_is_array_texture(gl_target);
 351       break;
 352    }
 353
 354    surf[0] = surftype << BRW_SURFACE_TYPE_SHIFT |
 355              format << BRW_SURFACE_FORMAT_SHIFT |
 356              (irb->mt->array_layout == ALL_SLICES_AT_EACH_LOD ?
 357                  GEN7_SURFACE_ARYSPC_LOD0 : GEN7_SURFACE_ARYSPC_FULL) |
 358              gen7_surface_tiling_mode(mt->tiling);
 359
 360    if (irb->mt->valign == 4)
 361       surf[0] |= GEN7_SURFACE_VALIGN_4;
 362    if (irb->mt->halign == 8)
 363       surf[0] |= GEN7_SURFACE_HALIGN_8;
 364
 365    if (is_array) {
 366       surf[0] |= GEN7_SURFACE_IS_ARRAY;
 367    }
 368
 369    assert(mt->offset % mt->cpp == 0);
 370    surf[1] = mt->bo->offset64 + mt->offset;
 371
 372    assert(brw->has_surface_tile_offset);
 373
 374    surf[5] = SET_FIELD(mocs, GEN7_SURFACE_MOCS) |
 375              (irb->mt_level - irb->mt->first_level);
 376
 377    surf[2] = SET_FIELD(irb->mt->logical_width0 - 1, GEN7_SURFACE_WIDTH) |
 378              SET_FIELD(irb->mt->logical_height0 - 1, GEN7_SURFACE_HEIGHT);
 379
 380    surf[3] = ((depth - 1) << BRW_SURFACE_DEPTH_SHIFT) |
 381              (mt->pitch - 1);
 382
 383    surf[4] = gen7_surface_msaa_bits(irb->mt->num_samples, irb->mt->msaa_layout) |
 384              min_array_element << GEN7_SURFACE_MIN_ARRAY_ELEMENT_SHIFT |
 385              (depth - 1) << GEN7_SURFACE_RENDER_TARGET_VIEW_EXTENT_SHIFT;
 386
 387    if (irb->mt->mcs_mt) {
 388       gen7_set_surface_mcs_info(brw, surf, offset,
 389                                 irb->mt->mcs_mt, true /* is RT */);
 390    }
 391
 392    surf[7] = irb->mt->fast_clear_color_value;
 393
 394    if (brw->is_haswell) {
 395       surf[7] |= (SET_FIELD(HSW_SCS_RED,   GEN7_SURFACE_SCS_R) |
 396                   SET_FIELD(HSW_SCS_GREEN, GEN7_SURFACE_SCS_G) |
 397                   SET_FIELD(HSW_SCS_BLUE,  GEN7_SURFACE_SCS_B) |
 398                   SET_FIELD(HSW_SCS_ALPHA, GEN7_SURFACE_SCS_A));
 399    }
 400
 401    drm_intel_bo_emit_reloc(brw->batch.bo,
 402                            offset + 4,
 403                            mt->bo,
 404                            surf[1] - mt->bo->offset64,
 405                            I915_GEM_DOMAIN_RENDER,
 406                            I915_GEM_DOMAIN_RENDER);
 407
 408    gen7_check_surface_setup(surf, true /* is_render_target */);
 409
 410    return offset;
 411 }
 412
 413 void
 414 gen7_init_vtable_surface_functions(struct brw_context *brw)
 415 {
 416    brw->vtbl.update_texture_surface = brw_update_texture_surface;
 417    brw->vtbl.update_renderbuffer_surface = gen7_update_renderbuffer_surface;
 418    brw->vtbl.emit_null_surface_state = gen7_emit_null_surface_state;
 419    brw->vtbl.emit_buffer_surface_state = gen7_emit_buffer_surface_state;
 420 }